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PCA9544ARGYR Datasheet(PDF) 6 Page - Texas Instruments |
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PCA9544ARGYR Datasheet(HTML) 6 Page - Texas Instruments |
6 / 27 page www.ti.com Interrupt Handling PCA9544A 4-CHANNEL I2C AND SMBus MULTIPLEXER WITH INTERRUPT LOGIC SCPS146C – OCTOBER 2005 – REVISED OCTOBER 2006 Table 1. Control Register Write (Channel Selection), Control Register Read (Channel Status)(1) INT3 INT2 INT1 INT0 D3 B2 B1 B0 COMMAND X X X X X 0 X X No channel selected X X X X X 1 0 0 Channel 0 enabled X X X X X 1 0 1 Channel 1 enabled X X X X X 1 1 0 Channel 2 enabled X X X X X 1 1 1 Channel 3 enabled No channel selected, 0 0 0 0 0 0 0 0 power-up default state (1) Only one channel may be selected at a time. The PCA9544A provides four interrupt inputs (one for each channel) and one open-drain interrupt output. When an interrupt is generated by any device, it is detected by the PCA9544A, and the interrupt output is driven low. The channel does not need to be active for detection of the interrupt. A bit also is set in the control register (see Table 2). Bits 4–7 of the control register correspond to channels 0–3 of the PCA9544A, respectively. Therefore, if an interrupt is generated by any device connected to channel 1, the state of the interrupt inputs is loaded into the control register when a read is accomplished. Likewise, an interrupt on any device connected to channel 0 causes bit 4 of the control register to be set on the read. The master then can address the PCA9544A and read the contents of the control register to determine which channel contains the device generating the interrupt. The master can reconfigure the PCA9544A to select this channel and locate the device generating the interrupt and clear it. Once the device responsible for the interrupt clears, the interrupt clears. It should be noted that more than one device can provide an interrupt on a channel, so it is up to the master to ensure that all devices on a channel are interrogated for an interrupt. The interrupt inputs can be used as general-purpose inputs if the interrupt function is not required. If unused, interrupt input(s) must be connected to VCC. Table 2. Control Register Read (Interrupt)(1) INT3 INT2 INT1 INT0 D3 B2 B1 B0 COMMAND 0 No interrupt on channel 0 X X X X X X X 1 Interrupt on channel 0 0 No interrupt on channel 1 X X X X X X X 1 Interrupt on channel 1 0 No interrupt on channel 2 X X X X X X X 1 Interrupt on channel 2 0 No interrupt on channel 3 X X X X X X X 1 Interrupt on channel 3 (1) Several interrupts can be active at the same time. For example, INT3 = 0, INT2 = 1, INT1 = 1, INT0 = 0 means that there is no interrupt on channels 0 and 3, and there is interrupt on channels 1 and 2. 6 Submit Documentation Feedback |
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