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RESET Input

Interrupt (INT) Output

Bus Transactions

Writes

1

2

SCL

3

4

5

6

7

8

SDA

A

A

A

Data 0

R/W

9

0

0

0

0

0

0

0

1

0.7

0.0

Data 1

1.7

1.0

A

S

1

1

1

0

1

A1 A0

0

P

Slave Address

Command Byte

Data to Port 0

Data to Port 1

Start Condition

Acknowledge

From Slave

Write to Port

Data Out from Port 1

Data Out from Port 0

Data Valid

Acknowledge

From Slave

Acknowledge

From Slave

PCA9539

WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

SCPS130D – AUGUST 2005 – REVISED MARCH 2007

signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original

setting, data is read from the port that generated the interrupt, or in a Stop event. Resetting occurs in the read

mode at the acknowledge (ACK) bit or not acknowledge (NACK) bit after the falling edge of the SCL signal. In a

Stop event, INT is cleared after the rising edge of SDA. Interrupts that occur during the ACK or NACK clock

pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the

I/Os after resetting is detected and is transmitted as INT.

Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output

cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the

state of the pin does not match the contents of the Input Port register. Because each 8-bit port is read

independently, the interrupt caused by port 0 is not cleared by a read of port 1, or vice versa.

Data is exchanged between the master and PCA9539 through write and read commands.

Data is transmitted to the PCA9539 by sending the device address and setting the least-significant bit to a logic

0 (see Figure 4 for device address). The command byte is sent after the address and determines which register

receives the data that follows the command byte.

The eight registers within the PCA9539 are configured to operate as four register pairs. The four pairs are input

ports, output ports, polarity inversion ports, and configuration ports. After sending data to one register, the next

data byte is sent to the other register in the pair (see Figure 6 and Figure 7). For example, if the first byte is sent

to Output Port 1 (register 3), the next byte is stored in Output Port 0 (register 2).

There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register

may be updated independently of the other registers.

Figure 6. Write to Output Port Registers

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