www.ti.com

Device Address

1

1

1

0

A1

A2

A0

Slave Address

R/W

Fixed

Hardware

Selectable

Control Register

Interrupt Bits

(Read Only)

Channel-Selection Bits

(Read/Write)

Enable Bit

INT3 INT2 INT1 INT0

B2

B1

B0

7

6

5

4

3

2

1

0

X

INT1

INT3

INT2

INT0

Control Register Definition

PCA9544A

WITH INTERRUPT LOGIC

SCPS146C – OCTOBER 2005 – REVISED OCTOBER 2006

Following a start condition, the bus master must output the address of the slave it is accessing. The address of

the PCA9544A is shown in Figure 1. To conserve power, no internal pullup resistors are incorporated on the

hardware-selectable address pins, and they must be pulled high or low.

Figure 1. PCA9544A Address

The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected,

while a logic 0 selects a write operation.

Following the successful acknowledgment of the slave address, the bus master sends a byte to the PCA9544A,

which is stored in the control register. If multiple bytes are received by the PCA9544A, it saves the last byte

Figure 2. Control Register

One or several SCn/SDn downstream pairs, or channels, are selected by the contents of the control register

(see Table 1). This register is written after the PCA9544A has been addressed. The three LSBs of the control

byte are used to determine which channel (or channels) is to be selected. When a channel is selected, the

lines are in a high state when the channel is made active, so that no false conditions are generated at the time

of connection. A stop condition always must occur right after the acknowledge cycle.

5

Submit Documentation Feedback