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PCA9548APWR Datasheet(PDF) 5 Page - Texas Instruments

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Part # PCA9548APWR
Description  8-CHANNEL I2C SWITCH WITH RESET
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
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PCA9548APWR Datasheet(HTML) 5 Page - Texas Instruments

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SDA
SCL
Start Condition
S
Stop Condition
P
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Data Output
by Transmitter
SCL From
Master
Start
Condition
S
1
2
8
9
Data Output
by Receiver
Clock Pulse for
Acknowledgment
NACK
ACK
PCA9548A
8-CHANNEL I2C SWITCH
WITH RESET
SCPS143B – OCTOBER 2006 – REVISED MARCH 2007
Any number of data bytes can be transferred from the transmitter to receiver between the start and the stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK)
after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line
high. In this event, the transmitter must release the data line to enable the master to generate a stop condition.
Figure 1. Definition of Start and Stop Conditions
Figure 2. Bit Transfer
Figure 3. Acknowledgment on I2C Bus
5
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