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MM74HC595 Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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MM74HC595 Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 10 page © 2004 Fairchild Semiconductor Corporation DS005342 www.fairchildsemi.com September 1983 Revised July 2004 MM74HC595 8-Bit Shift Registers with Output Latches General Description The MM74HC595 high speed shift register utilizes advanced silicon-gate CMOS technology. This device pos- sesses the high noise immunity and low power consump- tion of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. This device contains an 8-bit serial-in, parallel-out shift reg- ister that feeds an 8-bit D-type storage register. The stor- age register has 8 3-STATE outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial output (standard) pins for cascading. Both the shift register and storage register use positive-edge trig- gered clocks. If both clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register. The 74HC logic family is speed, function, and pin-out com- patible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Features s Low quiescent current: 80 µA maximum (74HC Series) s Low input current: 1 µA maximum s 8-bit serial-in, parallel-out shift register with storage s Wide operating voltage range: 2V–6V s Cascadable s Shift register has direct clear s Guaranteed shift frequency: DC to 30 MHz Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Top View Truth Table Order Number Package Number Package Description MM74HC595M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC595SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC595MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC595N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide RCK SCK SCLR G Function XX X H QA thru QH = 3-STATE X X L L Shift Register cleared Q’H = 0 X ↑ H L Shift Register clocked QN = Qn-1, Q0 = SER ↑ X H L Contents of Shift Register transferred to output latches |
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