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SN65C3222EDWG4 Datasheet(PDF) 6 Page - Texas Instruments |
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SN65C3222EDWG4 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 15 page www.ti.com RECEIVER SECTION Switching Characteristics (1) SN65C3222E ,, SN75C3222E 3-V TO 5.5-V MULTICHANNEL RS-232 LINE DRIVERS/RECEIVERS WITH ±15-kV ESD PROTECTION SLLS725A – JUNE 2006 – REVISED JULY 2006 abc Electrical Characteristics(1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5) PARAMETER TEST CONDITIONS MIN TYP(2) MAX UNIT VOH High-level output voltage IOH = –1 mA VCC – 0.6 VCC – 0.1 V VOL Low-level output voltage IOL = 1.6 mA 0.4 V VCC = 3.3 V 1.5 2.4 VIT+ Positive-going input threshold voltage V VCC = 5 V 1.8 2.4 VCC = 3.3 V 0.6 1.2 VIT– Negative-going input threshold voltage V VCC = 5 V 0.8 1.5 Vhys Input hysteresis (VIT+ – VIT–) 0.3 V IOZ Output leakage current EN = 1 ±0.05 ±10 µA ri Input resistance VI = ±3 V to ±25 V 3 5 7 k Ω (1) Test conditions are C1–C4 = 0.1 µF at V CC = 3.3 V ± 0.3 V; C1 = 0.047 µF, C2–C4 = 0.33 µF at VCC = 5 V ± 0.5 V. (2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TYP(2) UNIT tPLH Propagation delay time, low- to high-level output CL = 150 pF, See Figure 3 300 ns tPHL Propagation delay time, high- to low-level output CL = 150 pF, See Figure 3 300 ns ten Output enable time CL = 150 pF, RL = 3 kΩ, See Figure 4 200 ns tdis Output disable time CL = 150 pF, RL = 3 kΩ, See Figure 4 200 ns tsk(p) Pulse skew(3) See Figure 3 300 ns (1) Test conditions are C1–C4 = 0.1 µF at V CC = 3.3 V ± 0.3 V; C1 = 0.047 µF, C2–C4 = 0.33 µF at VCC = 5 V ± 0.5 V. (2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C. (3) Pulse skew is defined as |tPLH – tPHL| of each channel of the same device. 6 Submit Documentation Feedback |
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