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INPUT REFERENCE REQUIREMENTS

AC TIMING, SERIAL BUS INTERFACE

DIGITAL INTERFACE CHARACTERISTICS

AUXILIARY AND CONTROL

TRF1121

TRF1221

SLWS170A – APRIL 2005 – REVISED DECEMBER 2005

Conditions: Signal BW = 6 MHz nom, 15 dB maximum loss IF2 SAW filter. See Figure 19

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Reference frequency

18

MHz

Temperature stability

Customer requirements

PPM

HCMOS Output

4

4.5

5

Vpp

Reference Input Symmetry

Waveform Duty Cycle

40%

60%

Reference source pulse rise time

10% to 90% of maximum voltage transition

1

4

nsec

Reference Phase Noise at 10 k

Ω offset

–153

–150

dBc/Hz

(1)

Note that for source peak-to-peak voltages of less than 4 V and dc-component other than 2.5-V degradation of the close-in phase noise

may occur. For oscillators with no dc-component, a dc-voltage may be applied using a voltage divider (see the schematic) .

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Clock to data invalid

See Figure 7

10

ns

Data valid to clock

See Figure 7

10

ns

Clock pulse width high

See Figure 7

50

ns

Clock pulse width low

See Figure 7

50

ns

Clock to enable low

See Figure 7

10

ns

Enable low to clock

See Figure 7

10

ns

Enable pulse width

See Figure 7

10

ns

Conditions: Signal BW = 6 MHz nom, 15 dB maximum loss IF2 SAW filter. See Figure 19

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input high voltage

2.1

5

V

Input low voltage

0

0.8

V

Input high current

0

50

µA

Input low current

0

–50

µA

Input capacitance

3

pF

Output logic 1 voltage

0 to 100-

µA load

2.4

3.6

V

Output logic 1 impedance

18

k

Ω

Output low voltage

0 to –100-

µA load

0

0.4

V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

External VCO enable voltage

CMOS compatible Input. See Table 9

V

Lock detect voltage (PLL1)

CMOS compatible output (active high). See Table 9

V

VLD2

Lock Detect Voltage (PLL2)

CMOS compatible output (active high). See Table 9

V

IF Output On

High

TXON

IF Amp Enable

IF Output Off

Low

EXTLO2IP

High

On-chip VCO2A selection

Logic level applied to EXTLOIP and EXTLOIN pins to

EXTLO2IN

Low

select either on chip VCO 2A or 2B. Pullup resistor = 200

Ω

EXTLO2IP

Low

and pulldown resistor = 1 k

Ω.

On-chip VCO2B selection

EXTLO2IN

High

EXTLO2IP

Low

Logic Level applied to EXTLOIP and EXTLOIN pins to

On-chip VCO2 selection

select the external VCO2 input

EXTLO2IN

Low

6