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7242CBAZ Datasheet(PDF) 4 Page - Intersil Corporation |
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7242CBAZ Datasheet(HTML) 4 Page - Intersil Corporation |
4 / 10 page 4 FN2866.4 February 9, 2007 Test Circuit Application Information Operating Considerations Shorting the RC terminal or output terminals to VDD may exceed dissipation ratings and/or maximum DC current limits (especially at high supply voltages). There is a limitation of 50pF maximum loading on the TB I/O terminal if the timebase is being used to drive the counter section. If higher value loading is used, the counter sections may miscount. For greatest accuracy, use timing component values shown in Figure 8. For highest frequency operation it will be desirable to use very low values for the capacitor; accuracy will decrease for oscillator frequencies in excess of 200kHz. The timing capacitor should be connected between the RC pin and the positive supply rail, VDD, as shown in Figure 1. When system power is turned off, any charge remaining on the capacitor will be discharged to ground through a large internal diode between the RC node and VSS. Do NOT reference the timing capacitor to ground, since there is no high current path in this direction to safely discharge the capacitor when power is turned off. The discharge current from such a configuration could potentially damage the device. When driving the counter section from an external clock, the optimum drive waveform is a square wave with an amplitude equal to the supply voltage. If the clock is a very slow ramp triangular, sine wave, etc., it will be necessary to “square up” the waveform; this can be done by using two CMOS inverters in series, operating from the same supply voltage as the ICM7242. The ICM7242 is a non-programmable timer whose principal applications will be very low frequency oscillators and long range timers; it makes a much better low frequency oscillator/timer than a 555 or ICM7555, because of the on- chip 8-bit counter. Also, devices can be cascaded to produce extremely low frequency signals. Because outputs will not be ANDed, output inverters are used instead of open drain N-Channel transistors, and the external resistors used for the 2242 will not be required for the ICM7242. The ICM7242 will, however, plug into a socket for the 2242 having these resistors. The timing diagram for the ICM7242 is shown in Figure 1. Assuming that the device is in the RESET mode, which occurs on power up or after a positive signal on the RESET terminal (if TRIGGER is low), a positive edge on the trigger input signal will initiate normal operation. The discharge transistor turns on, discharging the timing capacitor C, and all the flip-flops in the counter chain change states. Thus, the outputs on terminals 2 and 3 change from high to low states. After 128 negative timebase edges, the ÷28 output returns to the high state. NOTE: 4. ÷21 and ÷28 outputs are inverters and have active pullups. VDD ÷21 (RC/2) OUTPUT 1 2 3 4 8 7 6 5 TIME BASE INPUT/OUTPUT R TRIGGER RESET C VDD ÷28 (RC/256) OUTPUT TIME BASE PERIOD = 1.0RC; 1s = 1M Ω x 1µF TRIGGER INPUT (TERMINAL 6) TIMEBASE INPUT (TERMINAL 8) ÷2 OUTPUT (TERMINAL 2) ÷128/256 OUTPUT (TERMINAL 3) (ASTABLE OR “FREE RUN” MODE) ÷128/256 OUTPUT (TERMINAL 3) OR “ONE SHOT” MODE) (MONOSTABLE 128RC 128RC 128RC FIGURE 1. TIMING DIAGRAMS OF OUTPUT WAVEFORMS FOR THE ICM7242 (COMPARE WITH FIGURE 5) OUTPUTS 1 2 3 4 8 7 6 5 >3/4 (V+) VDD fIN VDD fIN/2 fIN/256 <1/4 (V+) FIGURE 2. USING THE ICM7242 AS A RIPPLE COUNTER (DIVIDER) ICM7242 ICM7242 |
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