3

FN2914.6

November 19, 2004

Power Supply Rejection Ratio

∆V

Full

70

90

-

dB

NOTES:

4. Full power bandwidth guaranteed based on slew rate measurement using:

.

5. Refer to Test Circuits section of the data sheet.

Test Circuits and Waveforms

FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE TEST CIRCUIT

Horizontal Scale: 100ns/Div.

LARGE SIGNAL RESPONSE

Horizontal Scale: 100ns/Div

SMALL SIGNAL RESPONSE

FIGURE 2. SETTLING TIME TEST CIRCUIT

Electrical Specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

FPBW

Slew Rate

2

πVPEAK

-----------------------------

=

+

1.6k

Ω

OUT

400

Ω

200

Ω

IN

NOTES:

-

+5V

90%

10%

-5V

+1V

-1V

IN

OUT

+

0.001

µF

0.001

µF

1

µF

V+

1

µF

V-

400

Ω

1k

Ω

5k

Ω

2k

Ω

PROBE

MONITOR

SETTLE

POINT

NOTES:

9. Load Capacitance should be less than 10pF.

10. It is recommended that resistors be carbon composition and that

feedback and summing network ratios be matched to 0.1%.

11. Settle Point (Summing Node) capacitance should be less than

10pF. For optimum settling time results, it is recommended that

the test circuit be constructed directly onto the device pins. A

Tektronix 568 Sampling Oscilloscope with S-3A sampling heads

is recommended as a settle point monitor.

-

HA-5195