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HEF4094BF Datasheet(PDF) 2 Page - NXP Semiconductors |
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HEF4094BF Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 7 page January 1995 2 Philips Semiconductors Product specification 8-stage shift-and-store bus register HEF4094B MSI DESCRIPTION The HEF4094B is an 8-stage serial shift register having a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs O0 to O7. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive-going clock transitions. The data in each shift register stage is transferred to the storage register when the strobe (STR) input is HIGH. Data in the storage register appears at the outputs whenever the output enable (EO) signal is HIGH. Two serial outputs (Os and O’s) are available for cascading a number of HEF4094B devices. Data is available at Os on positive-going clock edges to allow high-speed operation in cascaded systems in which the clock rise time is fast. The same serial information is available at O’s on the next negative-going clock edge and provides cascading HEF4094B devices when the clock rise time is slow. Fig.1 Functional diagram. PINNING FAMILY DATA, IDD LIMITS category MSI See Family Specifications HEF4094BP(N): 16-lead DIL; plastic (SOT38-1) HEF4094BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4094BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America D data input EO output enable input CP clock input Os, O’s serial outputs STR strobe input O0 to O7 parallel outputs Fig.2 Pinning diagram. |
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