4-10

Description

The HI5800 is a 12-bit, two-step, sampling analog-to-digital

converter which uses a subranging technique with digital

error correction. As illustrated in the block diagram, it uses a

sample and hold front end, 7-bit, R-2R D/A converter which

is laser trimmed to 14 bits accuracy, a 7-bit BiCMOS flash

converter, precision bandgap reference, digital controller

and timing generator, error correction logic, output latches

and BiCMOS output drivers.

The falling edge of the convert command signal puts the

sample and hold (S/H) in the hold mode and the conversion

process begins. At this point the Interrupt Request (IRQ) line is

set high indicating that a conversion is in progress. The output

of the S/H circuit drives the input of the 7-bit flash converter

through a switch. After allowing the flash to settle, the

intermediate output of the flash is stored in the latches which

feed the D/A and error correction logic. The D/A reconstructs

the analog signal and feeds the gain amplifier whose summing

node subtracts the held signal of the S/H and amplifies the

residue by 32. This signal is then switched to the flash for a

second pass using the input switch. The output of the second

flash conversion is fed directly to the error correction which

reconstructs the twelve bit word from the fourteen bit input. The

logic also decodes the overflow bit and the polarity of the

overflow. The output of the error correction is then gated

through the read controller to the output drivers. The data is

ready on the bus as soon as the IRQ line goes low.

I/O Control Inputs

The converter has four active low inputs (CS, CONV, OE

and A0) and fourteen outputs (D0 - D11, IRQ and OVF). All

inputs and outputs are TTL compatible and will also interface

to the newer TTL compatible families. All four inputs are

CMOS high input impedance stages and all outputs are

BiMOS drivers capable of driving 100pF loads.

In order to initiate a conversion or read the data bus, CS should

be held low. The conversion is initiated by the falling edge of the

CONV command. The OE input controls the output bus directly

and is independent of the conversion process. The data on the

bus changes just before the IRQ goes low. Therefore if the OE

line is held low all the time, the data on the bus will change just

before the IRQ line goes low. The byte control signal A0 is also

independent of the conversion process and the byte can be

manipulated anytime. When A0 is low the 12-bits and overflow

word is read on the bus. The bus can also be hooked up such

that the upper byte (D11 - D4) is read when A0 is low. When A0

is high, the lower byte (D3 - D0) is output on the same eight

pins with trailing zeros.

In order to minimize switching noise during a conversion,

byte manipulations done using the A0 signal should be done

in the single shot mode and A0 should be changed during

the acquisition phase. For accuracy, allow sufficient time for

settling from any glitches before the next conversion.

Once a conversion is started, the converter will complete the

conversion and acquisition periods irrespective of the input

states. If during these cycles another convert command is

issued, it will be ignored until the acquire phase is complete.

Stand Alone Operation

The converter can be operated in a stand alone configuration

with bus inputs controlling the converter. The conversion will be

started on the negative edge of the convert (CONV) pulse as

long as this pulse is less than the converter throughput rate. If

the converter is given multiple convert commands, it will ignore

all but the first command until such time when the acquisition

period of the next cycle is complete. At this point it will start a

new conversion on the first negative edge of the input

command. This allows the converter to be synchronized to a

multiple of a faster external clock. The new output data of the

conversion is available on the same cycle at the negative edge

of the IRQ pulse and is valid until the next negative edge of the

IRQ pulse. Data may be accessed at any time during these

cycles. It should be noted that if the data bus is kept enabled all

the time (OE is low), then the data will be updating just before

the IRQ goes low. During this time, the data may not be valid

for a few nanoseconds.

Continuous Convert Mode

The converter can be operated at its maximum rate by taking

the CONV line low (supplying the first negative edge) and

holding it low. This enables the continuous convert mode.

During this time, at the end of the internal acquisition period,

the converter automatically starts a new conversion. The

data will be valid between the IRQ negative edges.

Note that there is no pipeline delay on the data. The output data

is available during the same cycle as the conversion and is

valid until the next conversion ends. This allows data access to

both previous and present conversions in the same cycle.

When initiating a conversion or a series of conversions, the

last signal (CS and CONV) to arrive dominates the function.

The same condition holds true for enabling the bus to read

the data (CS and OE). To terminate the bus operations, the

first signal (CS and OE) to arrive dominates the function.

Interrupt Request Output

The interrupt request line (IRQ) goes high at the start of each

conversion and goes low to indicate the start of the acquisition.

During the time that IRQ is high, the internal sample and hold is

in hold mode. At the termination of IRQ, the sample and hold

switches to acquire mode which lasts approximately 100ns. If

no convert command is issued for a period of time, the sample

and hold simply remains in acquire mode tracking the analog

input signal until the next conversion cycle is initiated. The IRQ

line is the only output that is not three-stateable.

The analog input of the HI5800 is coupled into the input

stage of the Sample and Hold amplifier. The input is a high

impedance bipolar differential pair complete with an ESD

protection circuit. Typically it has >3M

Ω input impedance.

With this high input impedance circuit, the HI5800 is easily

HI5800