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IG80C286-10 Datasheet(PDF) 4 Page - Intersil Corporation |
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IG80C286-10 Datasheet(HTML) 4 Page - Intersil Corporation |
4 / 60 page 4 Pin Descriptions The following pin function descriptions are for the 80C286 microprocessor. SYMBOL PIN NUMBER TYPE DESCRIPTION CLK 31 I SYSTEM CLOCK: provides the fundamental timing for the 80C286 system. It is divided by two inside the 80C286 to generate the processor clock. The internal divide-by-two circuitry can be synchro- nized to an external clock generator by a LOW to HIGH transition on the RESET input. D15 - D0 36 - 51 I/O DATA BUS: inputs data during memory, I/O, and interrupt acknowledge read cycles; outputs data during memory and I/O write cycles. The data bus is active HIGH and is held at high impedance to the last valid logic level during bus hold acknowledge. A23 - A0 7 - 8 10 - 28 32 - 43 O ADDRESS BUS: outputs physical memory and I/O port addresses. A23 - A16 are LOW during I/O transfers. A0 is LOW when data is to be transferred on pins D7 - D0 (see table below). The address bus is active High and floats to three-state off during bus hold acknowledge. BHE 1 O BUS HIGH ENABLE: indicates transfer of data on the upper byte of the data bus, D15 - D8. Eight-bit oriented devices assigned to the upper byte of the data bus would normally use BHE to condition chip select functions. BHE is active LOW and floats to three-state OFF during bus hold acknowledge. S1, S0 4, 5 O BUS CYCLE STATUS: indicates initiation of a bus cycle and along with M/IO and COD/lNTA, de- fines the type of bus cycle. The bus is in a TS state whenever one or both are LOW. S1 and S0 are active LOW and are held at a high impedance logic one during bus hold acknowledge. BHE AND A0 ENCODINGS BHE VALUE A0 VALUE FUNCTION 0 0 Word transfer 0 1 Byte transfer on upper half of data bus (D15 - D8) 1 0 Byte transfer on lower half of data bus (D7 - D0) 11 Reserved 80C286 BUS CYCLE STATUS DEFINITION COD/INTA M/IO S1 S0 BUS CYCLE INITIATED 0(LOW) 0 0 0 Interrupt acknowledge 00 0 1 Reserved 00 1 0 Reserved 0 0 1 1 None; not a status cycle 0 1 0 0 If A1 = 1 then halt; else shutdown 0 1 0 1 Memory data read 0 1 1 0 Memory data write 0 1 1 1 None; not a status cycle 1(HIGH) 0 0 0 Reserved 1 0 0 1 I/O read 1 0 1 0 I/O write 1 0 1 1 None; not a status cycle 11 0 0 Reserved 1 1 0 1 Memory instruction read 11 1 0 Reserved 1 1 1 1 None; not a status cycle 80C286 |
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