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HEF4510BF Datasheet(PDF) 8 Page - NXP Semiconductors |
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HEF4510BF Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 10 page January 1995 8 Philips Semiconductors Product specification BCD up/down counter HEF4510B MSI Minimum clock 5 95 45 ns see also waveforms Figs 6 and 7 pulse width; LOW 10 tWCPL 35 20 ns 15 25 15 ns Minimum PL 5 105 55 ns pulse width; HIGH 10 tWPLH 45 25 ns 15 35 15 ns Minimum MR 5 120 60 ns pulse width; HIGH 10 tWMRH 50 25 ns 15 40 20 ns Recovery time 5 130 65 ns for MR 10 tRMR 45 20 ns 15 30 15 ns Recovery time 5 150 75 ns for PL 10 tRPL 50 25 ns 15 30 15 ns Set-up times 5 100 50 ns Pn → PL 10 tsu 50 25 ns 15 40 20 ns 5 250 125 ns UP/DN → CP 10 tsu 100 50 ns 15 75 35 ns 5 120 60 ns CE → PL 10 tsu 40 20 ns 15 25 10 ns Hold times 5 10 −40 ns Pn → PL 10 thold 5 −20 ns 15 0 −20 ns 535 −90 ns UP/DN → CP 10 thold 15 −35 ns 15 15 −25 ns 520 −40 ns CE → CP 10 thold 5 −15 ns 15 5 −10 ns Maximum clock 5 5 10 MHz pulse frequency 10 fmax 12 24 MHz 15 17 34 MHz VDD V SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA |
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