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HD-6402 Datasheet(PDF) 4 Page - Intersil Corporation |
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HD-6402 Datasheet(HTML) 4 Page - Intersil Corporation |
4 / 7 page 4 Transmitter Operation The transmitter section accepts parallel data, formats the data and transmits the data in serial form on the Transmitter Register Output (TRO) terminal (See serial data format). Data is loaded from the inputs TBR1-TBR8 into the Transmitter Buffer Register by applying a logic low on the Transmitter Buffer Register Load (TBRL) input (A). Valid data must be present at least tset prior to and thold following the rising edge of TBRL. If words less than 8 bits are used, only the least significant bits are transmitted. The character is right justified, so the least significant bit corresponds to TBR1 (B). The rising edge of TBRL clears Transmitter Buffer Register Empty (TBRE). 0 to 1 Clock cycles later, data is transferred to the transmitter register, the Transmitter Register Empty (TRE) pin goes to a low state, TBRE is set high and serial data information is transmitted. The output data is clocked by Transmitter Register Clock (TRC) at a clock rate 16 times the data rate. A second low level pulse on TBRL loads data into the Transmitter Buffer Register (C). Data transfer to the transmitter register is delayed until transmission of the cur- rent data is complete (D). Data is automatically transferred to the transmitter register and transmission of that character begins one clock cycle later. Receiver Operation Data is received in serial form at the Receiver Register Input (RRI). When no data is being received, RRI must remain high. The data is clocked through the Receiver Register Clock (RRC). The clock rate is 16 times the data rate. A low level on Data Received Reset (DRR) clears the Data Receiver (DR) line (A). During the first stop bit data is transferred from the Receiver Register to the Receiver Buffer Register (RBR) (B). If the word is less than 8 bits, the unused most significant bits will be a logic low. The output character is right justified to the least significant bit RBR1. A logic high on Overrun Error (OE) indicates overruns. An overrun occurs when DR has not been cleared before the present character was transferred to the RBR. One clock cycle later DR is reset to a logic high, and Framing Error (FE) is evaluated (C). A logic high on FE indicates an invalid stop bit was received, a framing error. A logic high on Parity Error (PE) indicates a parity error. HD-6402 A B C D END OF LAST STOP BIT 1/2 CLOCK 0 TO 1 CLOCK DATA TBRL TBRE TRE TRO 1 FIGURE 1. TRANSMITTER TIMING (NOT TO SCALE) HD-6402 HD-6402 |
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