7

In the Write Cycle the falling edge of E latches the addresses

and S2 into on-chip registers. S2 must be latched in the low

state to enable the device. The write portion of the cycle is

defined as E, W, S1 being low and S2 being latched

simultaneously. The W line may go low at any time during the

cycle providing that the write pulse setup times (TWLEH and

TWLS1H) are met. The write portion of the cycle is terminated

on the first rising edge of either E, W, or S1.

If a series of consecutive write cycles are to be executed, the

W line may be held low until all desired locations have been

written. If this method is used, data setup and hold times must

be referenced to the first rising edge of E or S1. By positioning

the write pulse at different times within the E and S1 low time

(TELEH), various types of write cycles may be performed. If

the S1 low time (TS1LS1H) is greater than the W pulse, plus

an output enable time (TS1LQX), a combination read-write

cycle is executed. Data may be modified an indefinite number

of times during any write cycle (TELEH).

The HM-6551/883 may be used on a common I/O bus

structure by tying the input and output pins together. The

multiplexing is accomplished internally by the W line. In the

write cycle, when W goes low, the output buffers are forced to

a high impedance state. One output disable time delay

(TWLQZ) must be allowed before applying input data to the

bus.

(8) TAVEL

VALID

(8) TAVEL

NEXT

TELEH (6)

(11)

TWHDX (13)

TELEL (19)

(9) TS2LEL

TEHEL (7)

TELS2X

(9) TS2LEL

TWLEH (15)

TDVWH (12)

TWLWH (18)

TS1LWH (16)

TWLS1H (14)

-1

TIME

01

2

3

4

5

REFERENCE

A

E

S2

D

W

S1

(10)

TELAX

TEHEL (7)

DATA VALID

TELWH (17)

FIGURE 2. WRITE CYCLE

TRUTH TABLE

TIME

REFERENCE

INPUTS

OUTPUTS

FUNCTION

E

S1

S2

W

A

D

Q

-1

H

H

X

X

X

X

Z

Memory Disabled

0

X

L

X

V

X

Z

Cycle Begins, Addresses and S2 are

Latched

1

L

L

X

X

X

Z

Write Period Begins

2

L

L

X

X

V

Z

Data In is Written

3

X

X

H

X

X

Z

Write is Completed

4

H

H

X

X

X

X

Z

Prepare for Next Cycle (Same as -1)

5

X

L

X

V

X

Z

Cycle Ends, Next Cycle Begins (Same

as 0)

HM-6551/883

HM-6551/883