4

SYMBOL

PARAMETER

LIMITS

UNITS

TEST

CONDITIONS

HM-65262B-9

HM-65262-9

HM-65262C-9

MIN

MAX

MIN

MAX

MIN

MAX

READ CYCLE

(1)

TAVAX

Read/Cycle Time

70

-

85

-

85

-

ns

(Notes 1, 3)

(2)

TAVQV

Address Access Time

-

70

-

85

-

85

ns

(Notes 1, 3)

(3)

TELQV

Chip Enable Access Time

-

70

-

85

-

85

ns

(Notes 1, 3)

(4)

TELQX

Chip Enable Output Enable

Time

5-5-5-

ns

(Notes 2, 3)

(5)

TEHQX

Chip Disable Output Hold

Time

5-5-5-

ns

(Notes 2, 3)

(6)

TAXQX

Address Invalid Output Hold

Time

5-5-5-

ns

(Notes 2, 3)

(7)

TEHQZ

Chip Enable Output Disable

Time

-30-30

-30

ns

(Notes 2, 3)

WRITE CYCLE

(8)

TAVAX

Write Cycle Time

70

-

85

-

85

-

ns

(Notes 1, 3)

(9)

TELWH

Chip Selection to End of

Write

55

-

65

-

65

-

ns

(Notes 1, 3)

(10)

TWLWH

Write Enable Pulse Width

40

-

45

-

45

-

ns

(Notes 1, 3)

(11)

TAVWL

Address Setup Time

0

-

0

-

0

-

ns

(Notes 1, 3)

(12)

TWHAX

Address Hold Time

0

-

0

-

0

-

ns

(Notes 1, 3)

(13)

TDVWH

Data Setup Time

30

-

35

-

35

-

ns

(Notes 1, 3)

(14)

TWHDX

Data Hold Time

0

-

0

-

0

-

ns

(Notes 1, 3)

(15)

TWLQZ

Write Enable Output Disable

Time

-30-30

-30

ns

(Notes 2, 3)

(16)

TWHQX

Write Disable Output Enable

Time

0-0-0-

ns

(Notes 2, 3)

(17)

TAVWH

Address Valid to End of Write

55

-

65

-

65

-

ns

(Notes 1, 3)

(18)

TAVEL

Address Setup Time

0

-

0

-

0

-

ns

(Notes 1, 3)

(19)

TEHAX

Address Hold Time

0

-

0

-

0

-

ns

(Notes 1, 3)

(20)

TAVEH

Address Valid to End of Write

55

-

65

-

65

-

ns

(Notes 1, 3)

(21)

TELEH

Enable Pulse Width

55

-

65

-

65

-

ns

(Notes 1, 3)

(22)

TWLEH

Write Enable Pulse Setup

Time

40

-

45

-

45

-

ns

(Notes 1, 3)

(23)

TDVEH

Chip Setup Time

30

-

35

-

35

0

ns

(Notes 1, 3)

(24)

TEHDX

Data Hold Time

0

-

0

-

0

-

ns

(Notes 1, 3)

NOTES:

1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate

2. Tested at initial design and after major design changes.

HM-65262