January 1995

2

Philips Semiconductors

Product specification

BCD rate multiplier

HEF4527B

MSI

DESCRIPTION

The HEF4527B is a BCD rate multiplier with two buffered

an overriding asynchronous clear input (CL), a strobe input

(STR), a cascade input (CAS) and an active LOW count

enable input (CE).

The BCD rate multiplier provides an output pulse rate

based upon the BCD input number. For example, if 6 is the

BCD number, there will be six output pulses for every ten

clock input pulses. The output is clocked on the

negative-going transition of the clock.

When CE, STR, CAS, CL and PL are LOW, the rate pulses

pulses at TC and TC.

A HIGH on CL resets the counter, independent of all other

content of the counter.

A HIGH on PL sets the counter in the ‘9’ state and TC

becomes HIGH.

function table).

This device may be used to perform arithmetic operations.

For the add mode and multiply mode see Figs 5 and 6.

Schmitt-trigger action in the clock input makes the circuit

highly tolerant to slower clock rise and fall times.

See Family Specifications

Fig.1 Functional diagram.