January 1995

6

Philips Semiconductors

Product specification

Universal divider

HEF4751V

LSI

PROGRAMME DATA INPUT (see also Figs 3 and 4)

The programming process is timed and controlled by input

PC and PE. When the programme enable (PE) input is

HIGH; the positive edges of the programme clock (PC)

signal step through the internal programme counter in a

sequence of 8 states. Seven states define fetch periods,

each indicated by a LOW signal at one of the

data address signals may be used to address the external

programme source. The data fetched from the programme

is LOW in a fetch period an internal load pulse is

generated, the data is valid during this time and has to be

stable. When PE is LOW, the programming cyclus is

interrupted on the first positive edge of PC. On the next

negative edge at input PC fetch period 6 is entered. Data

may enter asynchronously in fetch period 6.

Ten blocks in the U.D. need programme input signals (see

concerned with the configuration of the U.D. and are

programmed in fetch period 6. The remaining blocks (RS0

to RS4 and C1) are programmed with number P,

These digits are formed by a substractor from two external

P=A

P=A

The numbers A and B, each consisting of six four bit digits

binary coded negative logic.

(SI = HIGH: borrow, SI = LOW: no borrow).

Counter C1 is automatically programmed with the most

is fully programmable by the use of pulse rate feedback.

Rate feedback is generated by the rate selectors RS4 to

programmed and configured via data B inputs. Counter C3

is programmed in fetch period 6 via data A inputs in

negative logic (except all HIGH is understood as: M = 16).

The counter C0 is a side steppable 10/11 counter

10/11 or 5/6 or 2/3 or 1 respectively. In the latter case

FEEDBACK TO PRESCALERS (see also Figs 5 and 6)

The counters C1, C0, C

−1 and C−2 are side-steppable

counters, i.e. its division ratio may be increased by one, by

applying a pulse to a control terminal for the duration of

one division cycle. Counter C2 has 10 states, which are

accessible as timing signals for the rate selectors RS1 to

U.D.) generates n of 10 basic timing periods an active

signal. Since n

≤ 9, 1 of 10 periods is always non-active. In

this period RS1 transfers the output of rate selector RS0,

Similarly, RS0 transfers RSH output during one period of

C3. Rate selector RSH is timed by C4 and programmed

always, if C4 is disabled, RSH transfers the LOW active

signal at input RI to RS0. If RI is not used it must be

connected to HIGH. The feedback output signals of RS1,

RS2 and RS3 are externally available as active LOW

prescaler needs a feedback signal, which is timed on one

of its own division cycles in a basic timing period. The

timing signal at OSY is LOW during the last U.D. input

period of a basic timing period and is suitable for timing of

the feedback for the last external prescaler. The

synchronization signal for a preceding prescaler is the

OR-function of the sync. input and sync. output of the

following prescaler (all sync. signals active LOW).