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HEF4751VT Datasheet(PDF) 6 Page - NXP Semiconductors |
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HEF4751VT Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 10 page January 1995 6 Philips Semiconductors Product specification Universal divider HEF4751V LSI PROGRAMME DATA INPUT (see also Figs 3 and 4) The programming process is timed and controlled by input PC and PE. When the programme enable (PE) input is HIGH; the positive edges of the programme clock (PC) signal step through the internal programme counter in a sequence of 8 states. Seven states define fetch periods, each indicated by a LOW signal at one of the corresponding data address outputs (OD0 to OD6). These data address signals may be used to address the external programme source. The data fetched from the programme source is applied to inputs A0 to A3 and B0 to B3. When PC is LOW in a fetch period an internal load pulse is generated, the data is valid during this time and has to be stable. When PE is LOW, the programming cyclus is interrupted on the first positive edge of PC. On the next negative edge at input PC fetch period 6 is entered. Data may enter asynchronously in fetch period 6. Ten blocks in the U.D. need programme input signals (see Fig.2). Four of these (C0b, C3, C4 and RSH) are concerned with the configuration of the U.D. and are programmed in fetch period 6. The remaining blocks (RS0 to RS4 and C1) are programmed with number P, consisting of six internal digits n0 to n5. P=(n5 ⋅ 104 + n4 ⋅ 103 + n3 ⋅ 102 + n2 ⋅ 10 + n1) ⋅ M + n0 These digits are formed by a substractor from two external numbers A and B and a borrow-in (bin). P=A − B − bin or if this result is negative; P=A − B − bin + M ⋅ 105. The numbers A and B, each consisting of six four bit digits n0A to n5A and n0B to n5B, are applied in fetch period 0 to 5 to the inputs A0 to A3 (data A) and B0 to B3 (data B) in binary coded negative logic. A = (n5A ⋅ 104 + n4A ⋅ 103 + n3A ⋅ 102 + n2A ⋅ 10 + n1A) ⋅ M + n0A. B=(n5B ⋅ 104 + n4B ⋅ 103 + n3B ⋅ 102 + n2B ⋅ 10 + n1B) ⋅ M + n0B. Borrow-in (bin) is applied via input SI in fetch period 0 (SI = HIGH: borrow, SI = LOW: no borrow). Counter C1 is automatically programmed with the most significant non-zero digit (nms) from the internal digits n5 to n2 of number P. The counter chain C − 2 to C1 (see Fig.3) is fully programmable by the use of pulse rate feedback. Rate feedback is generated by the rate selectors RS4 to RS0 and RSH, which are programmed with digits n4 to n0 and nh respectively. In fetch period 6 the fractional counter C3, half channel counter C4 and C0b are programmed and configured via data B inputs. Counter C3 is programmed in fetch period 6 via data A inputs in negative logic (except all HIGH is understood as: M = 16). The counter C0 is a side steppable 10/11 counter composed of an internal part C0b and an external part C0a. C0b is configured via B3 and B2 to a division ratio of 1 or 2 or 5 or 10/11; C0a must have the complementary ratio 10/11 or 5/6 or 2/3 or 1 respectively. In the latter case C0b comprises the whole C0 counter with internal feedback, C0a is then not required. The half channel counter C4 is enabled with B0 = HIGH and disabled with B0 = LOW. With C4 enabled, a half channel offset can be programmed with input B1 = HIGH, and no offset with B1 = LOW. FEEDBACK TO PRESCALERS (see also Figs 5 and 6) The counters C1, C0, C −1 and C−2 are side-steppable counters, i.e. its division ratio may be increased by one, by applying a pulse to a control terminal for the duration of one division cycle. Counter C2 has 10 states, which are accessible as timing signals for the rate selectors RS1 to RS4. A rate selector, programmed with n (n1 to n4 in the U.D.) generates n of 10 basic timing periods an active signal. Since n ≤ 9, 1 of 10 periods is always non-active. In this period RS1 transfers the output of rate selector RS0, which is timed by counter C3 and programmed with n0. Similarly, RS0 transfers RSH output during one period of C3. Rate selector RSH is timed by C4 and programmed with nh. In one of the two states of C4, if enabled, or always, if C4 is disabled, RSH transfers the LOW active signal at input RI to RS0. If RI is not used it must be connected to HIGH. The feedback output signals of RS1, RS2 and RS3 are externally available as active LOW signals at outputs OFB1, OFB2 and OFB3. Output OFB1 is intended for the prescaler at the highest frequency (if present), OFB2 for the next (if present) and OFB3 for the lowest frequency prescaler (if present). A prescaler needs a feedback signal, which is timed on one of its own division cycles in a basic timing period. The timing signal at OSY is LOW during the last U.D. input period of a basic timing period and is suitable for timing of the feedback for the last external prescaler. The synchronization signal for a preceding prescaler is the OR-function of the sync. input and sync. output of the following prescaler (all sync. signals active LOW). |
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