LPC47M112 datasheet(5/204 Pages) SMSC

Part #	LPC47M112

Description	Enhanced Super I/O Controller with LPC Interface

Download	204 Pages

Scroll/Zoom	100%

Manufacturer	SMSC [SMSC Corporation]

Direct Link	http://www.smsc.com

Logo

5 / 204 page

Enhanced Super I/O Controller with LPC Interface

Datasheet

SMSC DS – LPC47M112

Page 5

Rev. 02-16-07

DATASHEET

FIGURE 6 – MOUSE LATCH.....................................................................................................................................112

FIGURE 7 -GPIO FUNCTION ILLUSTRATION .........................................................................................................117

FIGURE 8 - POWER-UP TIMING ..............................................................................................................................178

FIGURE 9A - INPUT CLOCK TIMING .......................................................................................................................178

FIGURE 10 - OUPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS......................................................180

FIGURE 11 – INPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS.......................................................180

FIGURE 12 – I/O WRITE ...........................................................................................................................................181

FIGURE 13 – I/O READ.............................................................................................................................................181

FIGURE 14 – DMA REQUEST ASSERTION THROUGH NLDRQ ............................................................................182

FIGURE 15 – DMA WRITE (FIRST BYTE) ................................................................................................................182

FIGURE 16 – DMA READ (FIRST BYTE)..................................................................................................................182

FIGURE 17 – FLOPPY DISK DRIVE TIMING (AT MODE ONLY) .............................................................................183

FIGURE 18 – EPP 1.9 DATA OR ADDRESS WRITE CYCLE ...................................................................................184

FIGURE 19 – EPP 1.9 DATA OR ADDRESS READ CYCLE ....................................................................................185

FIGURE 20 – EPP 1.7 DATA OR ADDRESS WRITE CYCLE ...................................................................................186

FIGURE 21 – EPP 1.7 DATA OR ADDRESS READ CYCLE ....................................................................................187

FIGURE 22 - PARALLEL PORT FIFO TIMING...........................................................................................................189

FIGURE 23 - ECP PARALLEL PORT FORWARD TIMING ........................................................................................190

FIGURE 24 - ECP PARALLEL PORT REVERSE TIMING..........................................................................................191

FIGURE 25 - IRDA RECEIVE TIMING.......................................................................................................................192

FIGURE 26 - IRDA TRANSMIT TIMING ....................................................................................................................193

FIGURE 27 - AMPLITUDE SHIFT KEYED IR RECEIVE TIMING..............................................................................194

FIGURE 28 - AMPLITUDE SHIFT KEYED IR TRANSMIT TIMING ...........................................................................195

FIGURE 29 – SETUP AND HOLD TIME....................................................................................................................196

FIGURE 30 – SERIAL PORT DATA ..........................................................................................................................196

FIGURE 31 – JOYSTICK POSITION SIGNAL...........................................................................................................197

FIGURE 32 – JOYSTICK BUTTON SIGNAL .............................................................................................................197

FIGURE 33 – KEYBOARD/MOUSE RECEIVE/SEND DATA TIMING .......................................................................198

FIGURE 34– MIDI DATA BYTE .................................................................................................................................199

FIGURE 35 – FAN OUTPUT TIMING ........................................................................................................................199

FIGURE 36 – FAN TACHOMETER INPUT TIMING ..................................................................................................200

FIGURE 37 – LED OUTPUT TIMING ........................................................................................................................200

FIGURE 38 - 100 PIN 14X20MM QFP PACKAGE OUTLINE, 3.2 MM FOOTPRINT.................................................201

FIGURE 39 - XNOR-CHAIN TEST STRUCTURE......................................................................................................202

List of Tables

Table 1 - Super I/O Block Addresses ...........................................................................................................................20

Table 2 - Status, Data and Control Registers...............................................................................................................25

Table 3 - Tape Select Bits.............................................................................................................................................29

Table 4 - Internal 2 Drive Decode - Normal ...................................................................................................................29

Table 5 - Internal 2 Drive Decode - Drives 0 and 1 Swapped ........................................................................................30

Table 6 - Drive Type ID.................................................................................................................................................30

Table 7 - Precompensation Delays ..............................................................................................................................31

Table 8 - Data Rates ....................................................................................................................................................31

Table 9 - DRVDEN Mapping ........................................................................................................................................32

Table 10 - Default Precompensation Delays................................................................................................................32

Table 11 - FIFO Service Delay......................................................................................................................................34

Table 12 - Status Register 0 .........................................................................................................................................36

Table 13 - Status Register 1 .........................................................................................................................................37

Table 14 - Status Register 2 ........................................................................................................................................37

Table 15 - Status Register 3 ........................................................................................................................................38

Table 16 – Description of Command Controls .............................................................................................................41

Table 17 - Instruction Set .............................................................................................................................................44

Table 18 - Sector Sizes ................................................................................................................................................51

Table 19 - Effects of MT and N Bits ..............................................................................................................................51

Table 20 - Skip Bit vs Read Data Command.................................................................................................................51

Table 21 - Skip Bit vs. Read Deleted Data Command ...................................................................................................52

Table 22 - Result Phase...............................................................................................................................................53

Table 23 - Verify Command Result Phase ....................................................................................................................54

Table 24 - Typical Values for Formatting.......................................................................................................................55

Similar Part No. - LPC47M112

Manufacturer	Part #	Datasheet	Description
SMSC Corporation	LPC47M112	1Mb / 208P	ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE
	LPC47M112-MC	1Mb / 193P	ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE
	LPC47M112-MC	1Mb / 208P	ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE
	LPC47M112-MW	1Mb / 208P	ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE

More results

Similar Description - LPC47M112

Manufacturer	Part #	Datasheet	Description
SMSC Corporation	LPC47M112-MC	1Mb / 193P	ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE
	LPC47M112	1Mb / 208P	ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE
	LPC47B27X	1Mb / 196P	100 PIN ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE
	LPC47B272	1Mb / 195P	100 Pin Enhanced Super I/O Controller with LPC Interface
	LPC47S422	79Kb / 4P	Enhanced Super I/O with LPC Interface for Server Applications
	LPC47S42X	1Mb / 264P	ENHANCED SUPER I/O WITH LPC INTERFACE FOR SERVER APPLICATIONS
	LPC47M10X	1Mb / 188P	100 Pin Enhanced Super I/O Controller with LPC Interface for Consumer Applications
	LPC47M10X	244Kb / 5P	100 Pin Enhanced Super I/O Controller with LPC Interface for Consumer Applications
	LPC47N217N	410Kb / 5P	56-Pin Super I/O with LPC Interface
	LPC47B34X	645Kb / 250P	128 Pin Enhanced Super I/O with LPC Interface for Consumer Applications

More results

LPC47M112 Datasheet(PDF) 5 Page - SMSC Corporation

LPC47M112 Datasheet(HTML) 5 Page - SMSC Corporation

Similar Part No. - LPC47M112

Similar Description - LPC47M112

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL