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LAN91C96IQFP Datasheet(PDF) 3 Page - SMSC Corporation |
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LAN91C96IQFP Datasheet(HTML) 3 Page - SMSC Corporation |
3 / 109 page Non-PCI Single-Chip Full Duplex Ethernet Controller SMSC DS – LAN91C96I Page 3 Rev. 03-28-07 DATASHEET Table of Contents Chapter 1 General Description .............................................................................................................5 Chapter 2 Overview ............................................................................................................................... 6 Chapter 3 Pin Configurations ............................................................................................................... 9 3.1 Local Bus vs. Pin Requirements ....................................................................................................... 12 Chapter 4 Description of Pin Functions ............................................................................................. 14 4.1 Buffer Symbols .................................................................................................................................. 17 Chapter 5 Functional Description....................................................................................................... 19 5.1 Buffer Memory ................................................................................................................................... 20 5.2 Interrupt Structure ............................................................................................................................. 26 5.3 Reset Logic........................................................................................................................................ 27 5.4 Power Down Logic States ................................................................................................................. 27 Chapter 6 Packet Format in Buffer memory for Ethernet............................................................... 29 Chapter 7 Registers Map in I/O Space ............................................................................................... 32 7.1 I/O Space Access.............................................................................................................................. 33 7.2 I/O Space Registers Description ....................................................................................................... 34 7.2.1 Bank Select Register ..............................................................................................................................34 Chapter 8 Theory of Operation .......................................................................................................... 58 8.1 Typical Flow Of Events For Transmit (Auto Release =0).................................................................. 60 8.2 Typical Flow of Events for Transmit (Auto Release = 1)................................................................... 61 8.3 Typical Flow Of Events For Receive ................................................................................................. 62 8.4 Memory Partitioning .......................................................................................................................... 68 8.5 Interrupt Generation .......................................................................................................................... 68 8.6 Power Down ...................................................................................................................................... 70 Chapter 9 Functional Description of the Blocks................................................................................ 72 9.1 Memory Management Unit ................................................................................................................ 72 9.2 Arbiter ................................................................................................................................................ 72 9.3 Bus Interface ..................................................................................................................................... 73 9.4 Wait State Policy ............................................................................................................................... 73 9.5 Arbitration Considerations ................................................................................................................. 74 9.6 DMA Block......................................................................................................................................... 74 9.7 Packet Number FIFOs....................................................................................................................... 75 9.8 CSMA Block ...................................................................................................................................... 76 9.9 Network Interface .............................................................................................................................. 78 9.10 10BASE-T ...................................................................................................................................... 78 9.11 AUI ................................................................................................................................................. 78 9.12 Physical Interface........................................................................................................................... 79 9.13 Transmit Functions......................................................................................................................... 79 9.14 Transmit Drivers............................................................................................................................. 79 9.15 Receive Functions.......................................................................................................................... 79 Chapter 10 Board Setup Information ............................................................................................... 81 10.1 Diagnostic LEDs............................................................................................................................. 82 10.2 Bus Clock Considerations .............................................................................................................. 82 Chapter 11 Operation Description .................................................................................................... 84 11.1 Maximum Guaranteed Ratings*.....................................................................................................84 11.2 DC Electrical Characteristics ......................................................................................................... 85 Chapter 12 Timing Diagrams ............................................................................................................ 91 |
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