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LAN91C100 Datasheet(PDF) 5 Page - SMSC Corporation |
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LAN91C100 Datasheet(HTML) 5 Page - SMSC Corporation |
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5 / 101 page  5 DESCRIPTION OF PIN FUNCTIONSOF PIN FUNCTIONSPIN FUNCTIONS PQFP/TQFP PIN NO. NAME SYMBOL BUFFER TYPE DESCRIPTION 184 Write/nRea d W/nR I Input. Defines the direction of synchronous cycles. Write cycles when high, read cycles when low. 181 nVL Bus Access nVLBUS IP Input. When low the LAN91C100 synchronous bus interface is configured for VL Bus accesses. Otherwise the LAN91C100 is configured for EISA DMA burst accesses. Does not affect the asynchronous bus interface. 105 Local Bus Clock LCLK I Input. Used to interface synchronous buses. Maximum frequency is 50 MHz. Limited to 8.33 MHz for EISA DMA burst mode. 175 Asynchron- ous Ready ARDY OD16 Open drain output. ARDY may be used when interfacing asynchronous buses to extend accesses. Its rising (access completion) edge is controlled by the XTAL1 clock and therefore asynchronous to the host CPU or bus clock. 106 nSynchron- ous Ready nSRDY O16 Output. This output is used when interfacing synchronous buses and nVLBUS=0 to extend accesses. This signal remains normally inactive, and its falling edge indicates completion. This signal is synchronous to the bus clock LCLK. 109 nReady Return nRDYRTN I Input. This input is used to complete synchronous read cycles. In EISA burst mode it is sampled on falling LCLK edges, and synchronous cycles are delayed until it is sampled high. 176 187-189 Interrupt INT0-INT3 O24 Outputs. Only one of these interrupts is selected to be used; the other three are tri- stated. The selection is determined by the value of INT SEL1-0 bits in the Configuration Register. |
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