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USB97C202-MV-05 Datasheet(PDF) 11 Page - SMSC Corporation |
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USB97C202-MV-05 Datasheet(HTML) 11 Page - SMSC Corporation |
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11 / 19 page  USB 2.0 ATA/ATAPI Controller Datasheet SMSC USB97C202 Page 11 Revision 1.6 (01-09-07) DATASHEET MISC Crystal Input/External Clock Input XTAL1/ CLKIN ICLKx 12Mhz Crystal or external clock input. This pin can be connected to one terminal of the crystal or can be connected to an external 12Mhz clock when a crystal is not used. Crystal Output XTAL2 OCLKx 12Mhz Crystal This is the other terminal of the crystal, or left open when an external clock source is used to drive XTAL1/CLKIN. It may not be used to drive any external circuitry other than the crystal circuit. Clock Output CLKOUT O8 This pin produces a 30Mhz clock signal independent of the processor clock divider. It is held inactive and low whenever the internal processor clock is stopped or is being obtained from the ring oscillator. Internal ROM Enable ROMEN IP When left unconnected or tied high, the USB97C202 uses the internal ROM for program execution. When tied low, an external program memory should be connected to the memory/data bus. The state of this pin latched internally on the rising edge of nRESET. General Purpose I/O GPIO[1:7] IO20 These general purpose pins may be used either as inputs, edge sensitive interrupt inputs, or outputs. When using internal ROM mode, these pins have the following assignments: GPIO1: USB HS Indicator; active high. In part number USB97C202-MN-03 or later ROM codes, this pin also goes high during USB data transfers. GPIO2: Serial EEPROM (93LC66 type) Chip Select GPIO3: USB VBUS Detect Input GPIO4: Serial EEPROM Data In/OutGPIO5: ATA Drive Reset GPIO6: A16 control line for external program Flash memory when using firmware upgrade capability (external ROM operation only) GPIO7: Serial EEPROM Clock output RESET input nRESET IS This active low signal is used by the system to reset the chip. The active low pulse should be at least 100ns wide. Test input nTEST[0:2] IP These signals are used for testing the chip. User should normally leave them unconnected. For board continuity testing, all pads (except RBIAS, FSDP, USBDP, USBDM, FSDM, RTERM, XTAL1, XTAL2, LOOPFLTR and nTEST[0:2]) are included in an XNOR chain which is enabled by pulling nTEST2 low. nIOR is the output of the chain (the chain begins at pin 2) and will reflect the toggling of a signal on each pin. Circuit board continuity of the pin solder connections after assembly can be checked in this manner |
Similar Part No. - USB97C202-MV-05 |
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Similar Description - USB97C202-MV-05 |
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