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ADSP-BF544 Datasheet(PDF) 4 Page - Analog Devices |
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ADSP-BF544 Datasheet(HTML) 4 Page - Analog Devices |
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4 / 68 page  Rev. PrE | Page 4 of 68 | April 2007 ADSP-BF542/4/8/9 Preliminary Technical Data The ADSP-BF542/BF544/BF548 processors are completely code and pin compatible. They differ only with respect to their per- formance, on-chip memory, and selection of I/O peripherals. Specific performance, memory, and feature configurations, are shown in Table 1. The ADSP-BF549 is completely code compat- ible with the other ADSP-BF542/4/8/9 processors, and this processor is pin compatible, except for the location of the HWAIT pin. By integrating a rich set of industry-leading system peripherals and memory, Blackfin processors are the platform of choice for next-generation applications that require RISC-like program- mability, multimedia support and leading-edge signal processing in one integrated package. LOW-POWER ARCHITECTURE Blackfin processors provide world-class power management and performance. Blackfin processors are designed in a low power and low voltage design methodology and feature on-chip dynamic power management, the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption. Varying the voltage and frequency can result in a substantial reduction in power consumption, compared with just varying the frequency of operation. This translates into longer battery life for portable appliances. SYSTEM INTEGRATION The ADSP-BF542/4/8/9 processors are highly integrated sys- tem-on-a-chip solutions for the next generation of embedded network connected applications. By combining industry-stan- dard interfaces with a high performance signal processing core, users can develop cost-effective solutions quickly without the need for costly external components. The system peripherals include a high speed USB OTG (On-The-Go) controller with integrated PHY, CAN 2.0B controllers, TWI controllers, UART ports, SPI ports, serial ports (SPORTs), ATAPI controller, SD/SDIO controller, a real-time clock, a watchdog timer, LCD controller, and multiple enhanced parallel peripheral interfaces. ADSP-BF542/4/8/9 PROCESSOR PERIPHERALS The ADSP-BF542/4/8/9 processor contains a rich set of periph- erals connected to the core via several high bandwidth buses, providing flexibility in system configuration as well as excellent overall system performance (see Figure 1 on Page 1). The gen- eral-purpose peripherals include functions such as UARTs, SPI, TWI, timers with pulse width modulation (PWM) and pulse measurement capability, general purpose I/O pins, a real-time clock, and a watchdog timer. This set of functions satisfies a wide variety of typical system support needs and is augmented by the system expansion capabilities of the part. The ADSP-BF542/4/8/9 processor contains dedicated network com- munication modules and high-speed serial and parallel ports, an interrupt controller for flexible management of interrupts from the on-chip peripherals or external sources, and power manage- ment control functions to tailor the performance and power characteristics of the processor and system to many application scenarios. All of the peripherals, except for general-purpose I/O, CAN, TWI, real-time clock, and timers, are supported by a flexible DMA structure. There are also separate memory DMA channels dedicated to data transfers between the processor's various memory spaces, including external DDR and asynchronous memory. Multiple on-chip buses running at up to 133 MHz provide enough bandwidth to keep the processor core running along with activity on all of the on-chip and external peripherals. The ADSP-BF542/4/8/9 processor includes an on-chip voltage regulator in support of the ADSP-BF542/4/8/9 processor dynamic power management capability. The voltage regulator provides a range of core voltage levels when supplied from a sin- gle 2.70 V to 3.6 V input. The voltage regulator can be bypassed at the user's discretion. BLACKFIN PROCESSOR CORE As shown in Figure 2 on Page 5, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu- tation units process 8-bit, 16-bit, or 32-bit data from the register file. The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported register file and instruction constant fields. Each MAC can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. Signed and unsigned formats, rounding, and saturation are supported. The ALUs perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. In addition, many special instructions are included to accelerate various signal processing tasks. These include bit operations such as field extract and pop- ulation count, modulo 232 multiply, divide primitives, saturation and rounding, and sign/exponent detection. The set of video instructions include byte alignment and packing operations, 16- bit and 8-bit adds with clipping, 8-bit average operations, and 8- bit subtract/absolute value/accumulate (SAA) operations. Also provided are the compare/select and vector search instructions. For certain instructions, two 16-bit ALU operations can be per- formed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute register). By also using the second ALU, quad 16-bit operations are possible. The 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions. The program sequencer controls the flow of instruction execu- tion, including instruction alignment and decoding. For program flow control, the sequencer supports PC relative and indirect conditional jumps (with static branch prediction), and subroutine calls. Hardware is provided to support zero-over- head looping. The architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies. |
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