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ADSP-BF544 Datasheet(PDF) 8 Page - Analog Devices |
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ADSP-BF544 Datasheet(HTML) 8 Page - Analog Devices |
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8 / 68 page  Rev. PrE | Page 8 of 68 | April 2007 ADSP-BF542/4/8/9 Preliminary Technical Data • Non-Maskable Interrupt (NMI). The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shut- down of the system. • Exceptions. Events that occur synchronously to program flow (that is, the exception is taken before the instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause exceptions. • Interrupts. Events that occur asynchronously to program flow. They are caused by input pins, timers, and other peripherals, as well as by an explicit software instruction. Each event type has an associated register to hold the return address and an associated return-from-event instruction. When an event is triggered, the state of the processor is saved on the supervisor stack. The ADSP-BF542/4/8/9 processor event controller consists of two stages, the core event controller (CEC) and the system interrupt controller (SIC). The core event controller works with the system interrupt controller to prioritize and control all sys- tem events. Conceptually, interrupts from the peripherals enter into the SIC, and are then routed directly into the general-pur- pose interrupts of the CEC. Core Event Controller (CEC) The CEC supports nine general-purpose interrupts (IVG15–7), in addition to the dedicated interrupt and exception events. Of these general-purpose interrupts, the two lowest-priority inter- rupts (IVG15–14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the ADSP-BF542/4/8/9 processor. Table 3 describes the inputs to the CEC, identifies their names in the event vector table (EVT), and lists their priorities. System Interrupt Controller (SIC) The system interrupt controller provides the mapping and rout- ing of events from the many peripheral interrupt sources to the prioritized general-purpose interrupt inputs of the CEC. Although the ADSP-BF542/4/8/9 processor provides a default mapping, the user can alter the mappings and priorities of interrupt events by writing the appropriate values into the inter- rupt assignment registers (IAR). Table 4 describes the inputs into the SIC and the default mappings into the CEC. Table 3. Core Event Controller (CEC) Priority (0 is Highest) Event Class EVT Entry 0Emulation/Test Control EMU 1Reset RST 2 Non-Maskable Interrupt NMI 3Exception EVX 4Reserved — 5 Hardware Error IVHW 6 Core Timer IVTMR 7 General Interrupt 7 IVG7 8 General Interrupt 8 IVG8 9 General Interrupt 9 IVG9 10 General Interrupt 10 IVG10 11 General Interrupt 11 IVG11 12 General Interrupt 12 IVG12 13 General Interrupt 13 IVG13 14 General Interrupt 14 IVG14 15 General Interrupt 15 IVG15 Table 4. System Interrupt Controller (SIC) Peripheral IRQ (IRQ) Source IRQ ID GP IRQ (at Reset) Core IRQ ID PLL Wakeup IRQ 0 IVG7 0 DMAC0 Status (generic) 1 IVG7 0 EPPI0 Error IRQ 2 IVG7 0 SPORT0 Error IRQ 3 IVG7 0 SPORT1 Error IRQ 4 IVG7 0 SPI0 Status IRQ 5 IVG7 0 UART0 Status IRQ 6 IVG7 0 Real-Time Clock IRQ 7 IVG8 1 DMA12 IRQ (EPPI0) 8 IVG8 1 DMA0 IRQ (SPORT0 RX) 9 IVG9 2 DMA1 IRQ (SPORT0 TX) 10 IVG9 2 DMA2 IRQ (SPORT1 RX) 11 IVG9 2 DMA3 IRQ (SPORT1 TX) 12 IVG9 2 DMA4 IRQ (SPI0) 13 IVG10 3 DMA6 IRQ (UART0 RX) 14 IVG10 3 DMA7 IRQ (UART0 TX) 15 IVG10 3 Timer 8 IRQ 16 IVG11 4 Timer 9 IRQ 17 IVG11 4 Timer 10 IRQ 18 IVG11 4 Pin IRQ 0 (PINT0) 19 IVG12 5 Pin IRQ 1 (PINT1) 20 IVG12 5 MDMA Stream 0 IRQ 21 IVG13 6 MDMA Stream 1 IRQ 22 IVG13 6 Software Watchdog Timer IRQ 23 IVG13 6 DMAC1 Status (generic) 24 IVG7 0 SPORT2 Error IRQ 25 IVG7 0 SPORT3 Error IRQ 26 IVG7 0 MXVR Synchronous Data IRQ 27 IVG7 0 SPI1 Status IRQ 28 IVG7 0 SPI2 Status IRQ 29 IVG7 0 UART1 Status IRQ 30 IVG7 0 UART2 Status IRQ 31 IVG7 0 |
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