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ADSP-BF544 Datasheet(PDF) 11 Page - Analog Devices |
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ADSP-BF544 Datasheet(HTML) 11 Page - Analog Devices |
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11 / 68 page  ADSP-BF542/4/8/9 Preliminary Technical Data Rev. PrE | Page 11 of 68 | April 2007 external DDR, ROM, SRAM, and flash memory—with minimal processor intervention. Like peripheral DMAs, memory DMA transfers can be controlled by a very flexible descriptor-based methodology or by a standard register-based autobuffer mechanism. The memory DMA channels of the DMAC1 controller (MDMA2 and MDMA3) can be optionally controlled by the external DMA request input pins. When used in conjunction with the External Bus Interface Unit (EBIU), this so-called Handshaked Memory DMA (HMDMA) scheme can be used to efficiently exchange data with block-buffered or FIFO-style devices connected externally. Users can select whether the DMA request pins control the source or the destination side of the memory DMA. It allows control of the number of data transfers for memory DMA. The number of transfers per edge is pro- grammable. This feature can be programmed to allow memory DMA to have an increased priority on the external bus relative to the core. Host DMA Port Interface The Host DMA port (HOSTDP) facilitates a host device exter- nal to the ADSP-BF542/4/8/9 to be a DMA master and transfer data back and forth. The host device always masters the transac- tions and the processor is always a DMA slave device. The HOSTDP port is enabled through the peripheral access bus. Once the port has been enabled, the transaction are controlled by the external host. The external host programs standard DMA configuration words in order to send/receive data to any valid internal or external memory location. The Host DMA Port con- troller includes the following features: • Allows an external master to configure DMA read/write data transfers and read port status • Uses a flexible asynchronous memory protocol for its external interface • Allows an 8- or 16-bit external data interface to the host device • Supports half-duplex operation • Supports Little/Big Endian data transfers • Acknowledge mode allows flow control on host transactions • Interrupt mode guarantees a burst of FIFO depth host transactions REAL-TIME CLOCK The ADSP-BF542/4/8/9 processor Real-Time Clock (RTC) pro- vides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a 32.768 KHz crystal external to the ADSP-BF542/4/8/9 proces- sors. The RTC peripheral has dedicated power supply pins so that it can remain powered up and clocked even when the rest of the processor is in a low-power state. The RTC provides several programmable interrupt options, including interrupt per sec- ond, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a pro- grammed alarm time. The 32.768 KHz input clock frequency is divided down to a 1 Hz signal by a prescaler. The counter function of the timer consists of four counters: a 60-second counter, a 60-minute counter, a 24-hour counter, and an 32,768-day counter. When enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. There are two alarms: The first alarm is for a time of day. The second alarm is for a day and time of that day. The stopwatch function counts down from a programmed value, with one-second resolution. When the stopwatch is enabled and the counter underflows, an interrupt is generated. Like the other peripherals, the RTC can wake up the ADSP-BF542/4/8/9 processor from sleep mode upon generation of any RTC wakeup event. Additionally, an RTC wakeup event can wake up the ADSP-BF542/4/8/9 processor from deep sleep mode, and wake up the on-chip internal voltage regulator from the hibernate operating mode. Connect RTC pins RTXI and RTXO with external components as shown in Figure 4. WATCHDOG TIMER The ADSP-BF542/4/8/9 processor includes a 32-bit timer that can be used to implement a software watchdog function. A soft- ware watchdog can improve system availability by forcing the processor to a known state through generation of a hardware reset, non-maskable interrupt (NMI), or general-purpose inter- rupt, if the timer expires before being reset by software. The programmer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. Thereafter, the software must reload the counter before it counts to zero from the programmed value. This protects the system from remain- ing in an unknown state where software, which would normally reset the timer, has stopped running due to an external noise condition or software error. Figure 4. External Components for RTC RTXO C1 C2 X1 SUGGESTED COMPONENTS: ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) EPSON MC405 12 PF LOAD (SURFACE MOUNT PACKAGE) C1 = 22 PF C2 = 22 PF R1 = 10 M NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2 SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 PF. RTXI R1 |
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