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ISP1106W Datasheet(PDF) 5 Page - NXP Semiconductors |
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ISP1106W Datasheet(HTML) 5 Page - NXP Semiconductors |
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5 / 24 page  Philips Semiconductors ISP1105/1106/1107 Advanced USB transceivers Product data Rev. 06 — 30 November 2001 5 of 24 9397 750 08872 © Koninklijke Philips Electronics N.V. 2001. All rights reserved. 6.2 Pin description Table 3: Pin description Symbol[1] Pin Type Description ISP1105 HBCC16 ISP1106/7 HBCC16 ISP1106/7 TSSOP16 OE 113I input for output enable (CMOS level with respect to VCC(I/O), active LOW); enables the transceiver to transmit data on the USB bus RCV 224O differential data receiver output (CMOS level with respect to VCC(I/O)); driven LOW when input SUSPND is HIGH; the output state of RCV is preserved and stable during an SE0 condition VP 335O single-ended D + receiver output (CMOS level with respect to VCC(I/O)); for external detection of single-ended zero (SE0), error conditions, speed of connected device; driven HIGH when no supply voltage is connected to VCC(5.0) and Vreg(3.3) VM 446O single-ended D − receiver output (CMOS level with respect to VCC(I/O)); for external detection of single-ended zero (SE0), error conditions, speed of connected device; driven HIGH when no supply voltage is connected to VCC(5.0) and Vreg(3.3) SUSPND 557I suspend input (CMOS level with respect to VCC(I/O)); a HIGH level enables low-power state while the USB bus is inactive and drives output RCV to a LOW level MODE 6 I mode input (CMOS level with respect to VCC(I/O)); a HIGH level enables the differential input mode (VPO, VMO) whereas a LOW level enables a single-ended input mode (VO, FSE0). see Table 5 and Table 6 GND -[2] 6 8 - ground supply VCC(I/O) 779- supply voltage for digital I/O pins (1.65 to 3.6 V). When VCC(I/O) is not connected, the (D+, D−) pins are in three-state. This supply pin is totally independent of VCC(5.0) and Vreg(3.3) and must never exceed the Vreg(3.3) voltage. SPEED 8 8 10 I speed selection input (CMOS level with respect to VCC(I/O)); adjusts the slew rate of differential data outputs D + and D− according to the transmission speed: LOW: low-speed (1.5 Mbit/s) HIGH: full-speed (12 Mbit/s) D − 9 9 11 AI/O negative USB data bus connection (analog, differential); for low-speed mode connect to pin Vpu(3.3) via a 1.5 kΩ resistor D + 10 10 12 AI/O positive USB data bus connection (analog, differential); for full-speed mode connect to pin Vpu(3.3) via a 1.5 kΩ resistor VPO/VO 11 11 13 I driver data input (CMOS level with respect to VCC(I/O), Schmitt trigger); see Table 5 and Table 6 VMO/FSE0 12 12 14 I driver data input (CMOS level with respect to VCC(I/O), Schmitt trigger); see Table 5 and Table 6 |
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