ISP1581 datasheet(5/73 Pages) PHILIPS

Part #	ISP1581

Description	Universal Serial Bus 2.0 high-speed interface device

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Manufacturer	PHILIPS [NXP Semiconductors]

Direct Link	http://www.nxp.com

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Philips Semiconductors

ISP1581

USB 2.0 HS interface device

Objective speciﬁcation

Rev. 02 — 23 October 2000

5 of 73

9397 750 07648

6.2 Pin description

Table 2:

Pin description for LQFP64

Symbol [1]

Type [2]

Description

DGND

1

-

digital ground

VCC(5.0)

2

-

supply voltage (3.3 or 5.0 V)

AGND

3

-

analog ground

Vreg(3.3)

5

-

regulated supply voltage (3.3 V

± 10%) from internal

regulator; supplies internal analog circuits; used to connect

decoupling capacitor and 1.5 k

Ω pull-up resistor on D+ line

Remark: Cannot be used to supply external devices.

D

−

5

AI/O

USB D

− connection (analog)

D

+

6

AI/O

USB D

+ connection (analog)

RPU

7

AI

connection for external pull-up resistor for USB D

+ line;

must be connected to Vreg(3.3) via a 1.5 kΩ resistor

RREF

8

AI

connection for external bias resistor; must be connected to

ground via a 12.2 k

Ω (± 0.1%) resistor

MODE1

9

I

selects function of pin ALE/A0 (in Split Bus mode only):

0 — ALE function (address latch enable)

1 — A0 function (address/data indicator).

Remark: Connect to VCC(5.0) in Generic Processor mode.

RESET

10

I

reset input (Schmitt trigger); a LOW level produces an

asynchronous reset; connect to VCC for power-on reset

(internal POR circuit)

EOT

11

I

End Of Transfer input (programmable polarity, see

Table 37); used in DMA slave mode only

DREQ

12

I/O

DMA request (programmable polarity); direction depends

on the bit MASTER in the DMA Hardware register (DMA

master: input, DMA slave: output); see Table 37

DACK

13

I/O

DMA acknowledge (programmable polarity); direction of

depends on bit MASTER in the DMA Hardware register

(DMA slave: input, DMA master: output); see Table 37

DIOR

14

I/O

DMA read strobe (programmable polarity); direction

depends on bit MASTER in the DMA Hardware register

(DMA slave: input, DMA master: output); see Table 37

DIOW

15

I/O

DMA write strobe (programmable polarity); direction

depends on bit MASTER in the DMA Hardware register

(DMA slave: input, DMA master: output); see Table 37

INTRQ

16

I

interrupt request input from ATA/ATAPI peripheral

CS1

17

O

chip select output for ATAPI device

CS0

18

O

chip select output for ATAPI device

BUS_CONF/

DA0

19

I/O

during power-up: input to select the bus conﬁguration

0 — Split Bus mode; multiplexed 8-bit address/data bus on

AD[7:0], separate 8/16-bit DMA data bus on DATA[15:0]

1 — Generic Processor mode; separate 8-bit address on

AD[7:0], 16-bit DMA data bus on DATA[15:0].

normal operation: address output to select the task ﬁle

register of an ATAPI device

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