7

Delay Memory (Row Buffer) Mode

As seen by comparing Figures 8 and 10, the configuration

for this mode is nearly identical to the LUT mode. In this

mode, however, the counter is always providing the address

and the write function is always enabled.

In order to force this configuration to act as a row delay

register, the START signal must be used to reset the internal

counter each time a new row of pixels is being sampled.

Because of the inherent latency in the address and data

paths, the counter must be reset every N-4 cycles, where N

is the desired delay length. For example, if a delay from DIN

to DIO of ten cycles is desired, the START signal must be

set low every six cycles (see Figure 11). If the internal

address counter reaches its maximum count (1023), it holds

that value and further writes to the RAM are disabled.

Delay and Subtract Mode

This mode is similar to the Delay Memory mode, except the

input data is subtracted from the corresponding data stored

in RAM (See Figures 12 and 13).

Asynchronous 16/24 Modes

In the Asynchronous modes, the chip acts like a single port

RAM. In this mode, the user can read (access) any bin

location on the fly by simply setting the 10-bit IO address to

the desired bin location. The RAM is then read or written on

the following RD or WR pulse. A block diagram for this mode

is shown in Figure 14. Note that all registers and pipeline

stages are bypassed; START and CLK have no effect in

this mode.

Timing waveforms for this mode are also shown in Figure

15. During reading, the read address is latched (internally)

on the falling edge of RD. During write operations, the

address is latched on the falling edge of WR and data is

latched on the rising edge of WR. Note that reading and

writing occur on different ports, so that, in this mode, the

write port always latches its address and data values from

the WR signal, while the read port always uses RD for

latching.

FIGURE 9. LOOK UP TABLE MODE TIMING

CLK

PIN 0-9

START

DIO 0-23

DIN 0-23

DATA

0

OUTPUT

0

*

(WRITE)

ADDRESS

1

0

(READ)

1

234

5

1

23

0

RAM

Σ

IN

OUT

ADDRESS

DIO 0-23

CLK

START

CONTROL

DIO

I/F

COUNTER

“0”

DIN 0-23

RD

FIGURE 10. DELAY MEMORY BLOCK DIAGRAM

CLK

DIN 0-23

START

DIO 0-23

DATA

1

2

345

678

9

10

11

12

13

12

34

14

5

FIGURE 11. DELAY MEMORY MODE TIMING FOR ROW

LENGTH OF TEN

RAM

Σ

IN

OUT

ADDRESS

DIO 0-23

CLK

START

CONTROL

DIO

I/F

COUNTER

DIN 0-23

TWO’S

COMPLEMENT

RD

FIGURE 12. DELAY AND SUBTRACT BLOCK DIAGRAM

CLK

DIN 0-23

START

DIO 0-23

DATA

1

2

345

678

9

10 11 12

13

OUTPUT

1234

5

MODIFIED DATA

14

DATA 1

MINUS

DATA 7

DATA 2

MINUS

DATA 8

FIGURE 13. DELAY AND SUBTRACT MODE TIMING FOR

ROW LENGTH OF TEN

HSP48410