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HSP43216JC-52 Datasheet(PDF) 7 Page - Intersil Corporation |
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HSP43216JC-52 Datasheet(HTML) 7 Page - Intersil Corporation |
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7 / 20 page  7 FN3365.9 April 18, 2007 fS/4 Quadrature Up Convert Processor The fS/4 Quadrature Up Convert Processor provides the fS/4 spectral shift used to construct a real signal from a complex sample stream. The operation performed is equivalent to multiplying a quadrature data stream, i(n)+jq(n), by samples of a complex exponential, e-j(π/2)n, and outputting the real part of that mathematical operation as given below: Real { (i (n) + jq(n) ) e j (πn/2) } = Real {[i (n) cos ( πn/2) - q(n) sin (πn/2)] + j [i (n) sin ( πn/2) + q(n) cos (πn/2)]} = i (n) cos ( πn/2) - q(n) sin (πn/2) = i (n) cos ( πn/2) + q(n) sin (−πn/2) (EQ. 3) In the above operation, a positive fS/4 spectral shift is imparted on the quadrature input which causes the upper sideband of the resulting real output to be defined by the spectral content of the input signal as shown in Figure 3. For added flexibility, the Up Convert processor may be configured to impart a negative fS/4 shift on the quadrature input which generates a real output whose lower sideband is defined the spectrum of the quadrature input as shown in Figure 4. The state of the USB/LSB control input determines the direction of the spectral shift. If this input is set “High”, a positive fS/4 shift is introduced by the Up Convert Processor. If USB/LSB is asserted “Low”, a negative fS/4 spectral shift is introduced. FIGURE 3. 0fS/4 -fS/4 -fS/2 fS/2 0fS/4 -fS/4 -fS/2 fS/2 fS/4 POSITIVE SHIFT: UP CONVERSION FIGURE 4. 0fS/4 -fS/4 -fS/2 fS/2 0fS/4 -fS/4 -fS/2 fS/2 fS/4 NEGATIVE SHIFT: DOWN CONVERSION The Up Convert Processor implements the up convert operation by multiplying the in-phase and quadrature samples on the upper and lower processing legs by the nonzero sine and cosine terms in the above expression. The resulting data is then multiplexed together in the Output Flow Controller to yield the real output sample stream. The SYNC control input may be used to align the zero degree phase of the Up Convert LO with a particular input sample as described in the Operational Modes Section. The Up Convert Processor also scales the data streams output from the Filter Processor as required by the operational mode. In the modes which employ interpolation, the Up Convert Processor scales the Filter Processor’s output by two to compensate for the attenuation of one half caused by the interpolation process. In down convert and decimate mode, the filter processor output is also scaled by two to compensate for the attenuation introduced by the down covert process. The scaling operations performed are summarized in Table 4. SCALE FACTORS APPLIED BY UP CONVERT PROCESSOR vs MODE TABLE 4. MODE SCALE FACTOR Decimate by Two (MODE1-0 = 00) 1.0 Interpolate by Two (MODE1-0 = 01) 2.0 Down Convert and Decimate (MODE1-0 = 10) 2.0 Quadrature to Real (MODE1-0 = 11) 2.0 Output Data Flow Controller The Output Flow Controller routes data to the AOUT0-15 and BOUT0-15 output depending on mode of operation. In decimate by two mode (MODE1-0 = 00), output from the filter processor’s polyphase branches are summed and output through AOUT0-15. In Down Convert and Decimate mode (MODE1-0 = 10), real and imaginary data streams produced by the down convert process pass are output directly to AOUT0-15 and BOUT0-15 respectively. In the two modes using interpolation, MODE1-0 = 01 or 11, with internal multiplexing enabled, INT/EXT set high, data sam ples output from the polyphase branches are internally multiplexed into a single stream and output via AOUT0-15. If a mode using interpolation is specified together with external multiplexing, INT/EXT set low, the data stream multiplexing is performed off chip and the data on the upper and lower processing legs is output through AOUT0-15 and BOUT0-15. The Output Data Flow Controller also sets the binary format and precision of the two 16-bit outputs. The data format is specified as either two’s complement (FMT input low) or offset binary (FMT input high). The precision of the output data is set from 8-bits to 16-bits via the round control inputs, RND2-0. The RND2-0 inputs round the output data to a precision ranging from 8-bits to 16-bits as specified in Table 5. Saturation logic is incorporated in the output flow controller to insure that numerical growth associated with a worst case signal input or rounding condition saturates to a 16-bit value. HSP43216 |
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