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HI7131 Datasheet(PDF) 11 Page - Intersil Corporation |
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HI7131 Datasheet(HTML) 11 Page - Intersil Corporation |
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11 / 25 page  11 HI7131/33 vs ICL7136/37 Figure 5 shows the analog front end block diagram of both HI7131/33 and ICL7136/37. The difference is the common reference voltage generator connection and 2 extra analog switches in the ICL7136. The HI7131 architecture uses the INLO as the reference point of the integrator (non-inverting input of the integrator amplifier) in all the phases of the con- version cycle. The ICL7136 uses INLO as a reference point only during integration cycle and COMMON pin is used as the integrator reference point during auto-zero, deintegrate, and zero integrate phases. The circuit configuration of the HI7131 results in a superior 120dB rejection of DC common mode on the inputs. How- ever, the HI7131 has reduced AC common mode noise rejection, since the noise on the INLO input can cause errors during the deintegration phase. The circuit configuration of the ICL7136 is unaffected by the AC noise riding on the inputs, but the DC common mode rejection on the input is only 86dB. Analog Section Description Figure 5A shows a simplified diagram of the analog section of the HI7131 and HI7133. The circuit performs basic phases of dual slope integration. Furthermore, the device incorporates 2 additional phases called “Auto-Zero” and “Zero Integrate”. The device accepts differential input signals and reference voltages. Also, there is a reference voltage generator which sets the COMMON pin 2.8V below the V+ supply. A complete conversion cycle is divided into the following four phases: 1. Auto-Zero (A/Z) 2. Signal Integrate (INT) 3. Deintegrate or Reference Integrate (DE ±) 4. Zero Integrate (ZI) Digitally controlled analog switches direct the appropriate signals for each phase of the conversion. Auto-Zero Phase During auto-zero three things occur. First, IN HI is discon- nected from the device internal circuitry and internally shorted to IN LO. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor CAZ and integrating capacitor CINT to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the A/Z accu- racy is limited only by the noise of the system. In any case, the offset referred to the input is less than 10 µV. Signal Integrate Phase During signal integrate the auto-zero loop is opened and the FIGURE 93B. ICL7136 AND ICL7137 ANALOG SECTION FUNCTIONAL DIAGRAM FIGURE 93. HI7131, HI7133 vs ICL7136, ICL7137 ANALOG SECTIONS DE- DE+ VCOMMON GENERATOR POLARITY FLIP-FLOP ZERO CROSSING DETECTOR V - 26 CINT CAZ RINT BUFF A-Z INT V+ - + AZ COMPARATOR INHI COMMON INLO 31 32 30 DE- DE+ INT AZ 34 CREF+ 36 REFHI CREF REFLO 35 AZ AND ZI AZ AND ZI ZI INPUT HIGH 33 CREF- 28 29 27 V + TO DIGITAL SECTION AZ AND DE ± AND ZI V - INTEGRATOR 1 - + - + HI7131, HI7133 |
Similar Part No. - HI7131_02 |
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Similar Description - HI7131_02 |
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