TRANSMIT DATA FIFO (Write only) Write Address: X010

MIL-STD-1553 Message Data Word 15:0

15 14 13 12 11 10

9876543210

MSB

LSB

RECEIVE DATA FIFO (Read only) Read Address: 0100

MIL-STD-1553 Message Data Word 15:0

15 14 13 12 11 10

9876543210

MSB

LSB

MSB

LSB

15 14 13 12 11 10

9876543210

1

0

XX

X

0

REGISTER FORMATS (BC Mode)

HI-6110 (BUS CONTROLLER MODE)

CONTROL REGISTER (R/W) Write Address: X1XX, Read Address: 1100

The Control Register settings determine HI-6110 operating

mode, clock frequency and the bus enabled for transmit. It can

also be used to address registers for read/write operations, to

assert master reset, and to initiate MIL-STD-1553 message

sequences.

The Transmit Data FIFO is 32-words deep and holds MIL-

STD-1553 message data. The FIFO is cleared on Master

Reset.

Message data to be transmitted by the BC may be loaded into

the TRANSMIT DATA FIFO by the host prior to BCSTART.

Any data word must be loaded before mid-parity bit for the

1553 word it follows. Words are transmitted in the order they

are loaded.

The Receive Data FIFO is 32-words deep and holds MIL-

STD-1553 message data. The FIFO is cleared by Master

Reset or when BCSTART occurs.

All MIL-STD-1553 data words received by the BC are stored in

the Receive DATA FIFO. A low FFEMPTY flag (output pin or

Status register bit) means message data is available to be

read by the host. Successive data reads cause FFEMPTY to

go high when the last word is read.

HOLT INTEGRATED CIRCUITS

5

BIT

NAME

FUNCTION

15

-

Not used in BC mode

14

REPTO

Controls the time-out which causes the No Response Error.

0

17 usec Gap (equivalent to 57 usec for 5.2.1.7 of the RT Validation Test Plan)

1

131 usec Gap

13

-

12

CLKSEL

10 - 7

RA3:0

Register Address for HI-6110 register and data read and write operations. The register address is defined by

the logical OR of these bits and their corresponding input pins. Writting Control Register bits 10:7 to 0000 is

necessary if the RA0 - RA3 input pins are used for HI-6110 register addressing.

6-

5 - 4

TRB, TRA

BC

d

T

3 - 2

RTMODE,

HI-6110 mode select bits. These Control Register bits are logically OR'ed with their corresponding input pins,

BCMODE

allowing the user to select 1553 operating mode under either hardware or software control:

Not used in BC mode

Selects the frequency of the HI-6110 external CLK input, as follows:

CLKSEL

Value

0

24 MHz

1

12 MHz

11

Reserved

This bit must be written to “0”.

Not used in BC mode

Setting either TRA or TRB to "1" enables transmit on MIL-STD-1553 BUS A or BUS B. Setting both TRA and

TRB selects neither bus. The

protocol engine connects to the selected, active bus. The 1553 receiver,

Manchester ecoder and RCV output signal are still operational on the inactive bus. Valid words received on the

inactive bus can be read without changing active bus by reading the Bus A Word or Bus B Word register.

NOTE:

he TXINHA and TXINHB input pins can override bus enablement.

RTMODE

BCMODE

1553 OPERATING MODE

0

0

Bus Monitor (MT), with assigned RT address

0

1

Bus Controller (BC)

1

0

Remote Terminal (RT)

1

1

Bus Monitor (MT), without assigned RT address

1

BCSTART

If initially reset, writing a "1" to this bit initiates a BC message sequence. This bit should be reset before next

message.

0

MR

Master Reset. Writing "1" and then “0” to this bit performs the same function as pulsing the MR pin. All register

and data FIFOs are cleared when master reset is asserted. The Control Register is the exception; it is not

affected by Master Reset.