FUNCTIONAL DESCRIPTION (cont.)

TRANSMITTER

A block diagram of the transmitter section is shown in Figure 3.

The FIFO is loaded sequentially by first pulsing

to load byte 1

and then

to load byte 2. The control logic automatically loads

the 31 bit word in the next available position of the FIFO. If TX/R,

the transmitter ready flag, is high (FIFO empty), then 8 words,

each 31 bits long, may be loaded. If TX/R is low, then only the

available positions may be loaded. If all 8 positions are full, the

FIFO ignores further attempts to load data.

When ENTX goes high, enabling transmission, the FIFO

positions are incremented with the top register loading into the

data transmission shift register. Within 2.5 data clocks the first

data bit appears at either 429DO or

. The 31 bits in the

data transmission shift register are presented sequentially to the

outputs in the ARINC 429 format with the following timing:

ARINC DATA BIT TIME

10 Clocks

80 Clocks

DATA BIT TIME

5 Clocks

40 Clocks

NULL BIT TIME

5 Clocks

40 Clocks

WORD GAP TIME

40 Clocks

320 Clocks

The word counter detects when all loaded positions are

transmitted and sets the transmitter ready flag, TX/R, high.

FIFO OPERATION

DATA TRANSMISSION

PL1

PL2

429DO

HIGH SPEED

LOW SPEED

TRANSMITTER PARITY

Control register bit BD04 (PAREN) enables parity bit insertion into

transmitter data bit 32. Parity is always inserted if DBCEN is open

or high. If DBCEN is low, logic 0 on PAREN inserts data on bit 32,

and logic 1 on PAREN inserts parity on bit 32.

HI-3282

The parity generator counts the ONES in the 31-bit word. If the BD12

control word bit is set low, the 32nd bit transmitted will make parity

odd. If the control bit is high, the parity is even.

If the BD05 control word bit is set low, 429DO or

are internally

connected to the receivers inputs, bypassing the interface circuitry.

Data to Receiver 1 is as transmitted and data to Recevier 2 is the

complement. 429DO and

outputs remain active during self

test.

The two receivers are independent of the transmitter. Therefore,

control of data exchanges is strictly at the option of the user. The only

restrictions are:

1. The received data may be overwritten if not retrieved within

one ARINC word cycle.

2. The FIFO can store 8 words maximum and ignores attempts

to load addition data if full.

3. Byte 1 of the transmitter data must be loaded first.

4. Either byte of the received data may be retrieved first. Both

bytes must be retrieved to clear the data ready flag.

5. After ENTX, transmission enable, goes high it cannot go low

until TX/R, transmitter ready flag, goes high. Otherwise, one

ARINC word is lost during transmission.

SELF TEST

SYSTEM OPERATION

429DO

429DO

MASTER RESET (

)

MR

On a Master Reset data transmission and reception are immedi-

ately terminated, the transmit FIFO and receivers cleared as are

the transmit and receive flags. The Control Register is not affected

by a Master Reset.

CONTROL REGISTER

BIT BD13

FIGURE 3.

TRANSMITTER BLOCK DIAGRAM

DATA

CLOCK

PL1

PL2

CLK

TX CLK

PARITY

GENERATOR

DATA AND

NULL TIMER

SEQUENCER

BIT

AND

WORD GAP

COUNTER

START

SEQUENCE

WORD COUNTER

AND

FIFO CONTROL

INCREMENT

WORD COUNT

DATA CLOCK

DIVIDER

FIFO

LOADING

SEQUENCER

429DO

429DO

8X31FIFO

31 BIT PARALLEL

LOAD SHIFT REGISTER

BIT CLOCK

WORD CLOCK

ADDRESS

LOAD

DATA BUS

TX/R

ENTX

CONTROL REGISTER BD04, BD12

DBCEN

HOLT INTEGRATED CIRCUITS

5