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HI-3282PJTF Datasheet(PDF) 4 Page - Holt Integrated Circuits |
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HI-3282PJTF Datasheet(HTML) 4 Page - Holt Integrated Circuits |
4 / 13 page RECEIVER LOGIC OPERATION BIT TIMING Figure 2 shows a block diagram of the logic section of each receiver. The ARINC 429 specification contains the following timing specification for the received data: 100K BPS ± 1% 12K -14.5K BPS 1.5 ± 0.5 µsec 10 ± 5 µsec 1.5 ± 0.5 µsec 10 ± 5 µsec 5 µsec ± 5% 34.5 to 41.7 µsec BIT RATE PULSE RISE TIME PULSE FALL TIME PULSE WIDTH HIGH SPEED LOW SPEED RECEIVER PARITY The receiver parity circuit counts Ones received, including the parity bit, ARINC bit 32. If the result is odd, then "0" will appear in the 32nd bit. Once 32 valid bits are recognized, the receiver logic generates an End of Sequence (EOS). If the receiver decoder is enabled and the 9th and 10th ARINC bits match the control word program bits or if the receiver decoder is disabled, then EOS clocks the data ready flag flip flop to a "1", or (or both) will go low. The data flag for a receiver will remain low until after ARINC bytes from that receiver are retrieved. This is accomplished by activating with SEL, the byte selector, low to retrieve the first byte and activating with SEL high to retrieve the second byte. RETRIEVING DATA D/R1 D/R2 EN EN both FUNCTIONAL DESCRIPTION (cont.) SEL EN D/R DECODER CONTROL BITS / MUX CONTROL LATCH ENABLE CONTROL 32 TO 16 DRIVER 32 BIT LATCH 32 BIT SHIFT REGISTER TO PINS CONTROL BIT BD14 CLOCK OPTION CLOCK CLK BIT COUNTER AND END OF SEQUENCE PARITY CHECK 32ND BIT DATA BIT CLOCK EOS WORD GAP WORD GAP TIMER BIT CLOCK END START SEQUENCE CONTROL ERROR CLOCK ERROR DETECTION SHIFT REGISTER SHIFT REGISTER NULL ZEROS SHIFT REGISTER ONES EOS BITS 9 & 10 FIGURE 2. RECEIVER BLOCK DIAGRAM HI-3282 EN1 EN2 retrieves data from receiver 1 and retrieves data from receiver 2. If another ARINC word is received and a new EOS occurs before the two bytes are retrieved, the data is overwritten by the new word. INTERNAL LIGHTNING PROTECTION (-10 Only) APPLICATION NOTE 300 The HI-3282-10 configurations are similar to the HI-3282 except that the ARINC inputs are internally lightning protected to DO-160D, Level 3 through 10 Kohm resistors that be connected in series with each input from the ARINC bus. The design of the HI-3282-10 device requires the external 10 Kohm series resistors for proper ARINC level detection. The typical 10 volt differential signal is translated and input to a window comparator and latch. The comparator levels are set so that, with the external 10 Kohm resistors, they are just below the standard 6.5 V minimum ARINC data threshold and just above the 2.5 V maximum ARINC null threshold. The receivers of the HI-3282-10 when used with external 10 Kohm resistors will withstand DO-160D, Level 3, waveforms 3, 4 and 5A. No additional lightning protection circuit is necessary. Please refer to the Holt AN-300 Application Note for additional information and recommendations on lightning protection of Holt Line Drivers and Receivers. must HOLT INTEGRATED CIRCUITS 4 |
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Similar Description - HI-3282PJTF |
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