REPEATER OPERATION

The repeater mode of operation allows a data word that has been

received by the HI-3282 to be placed directly into its FIFO for

transmission. After a 32-bit word has been shifted into the receiver

shift register, the

flag will go low. A logic "0" is placed on the SEL

line and

is strobed. This is the same procedure as for normal

receiver operation and it places the lower byte (16) of the data word

on the data bus. By strobing

at the same time as

D/R

EN

PL1

EN, the byte

FUNCTIONAL DESCRIPTION (cont.)

will also be placed into the transmitter FIFO. SEL is then taken high

and

is strobed again to place the upper byte of the data word on

the data bus. By strobing

at the same time as

, the second

byte will also be placed into the FIFO. The data word is now ready to

be transmitted according to the parity programmed into the control

word register.

In normal operation, either byte of a received data word may be read

from the receiver latches first by use of SEL input. During repeater

operation however, the lower byte of the data word must be read

first. This is necessary because, as the data is being read, it is also

being loaded into the FIFO and the transmitter FIFO is always

loaded with the lower byte of the data word first.

EN

PL2

EN

DATA RATE - EXAMPLE PATTERN

429DO

429DO

ARINC BIT

NULL

DATA

DATA

DATA

NULL

NULL

WORD GAP

BIT 1

NEXT WORD

BIT 32

BIT 31

BIT 30

LOADING CONTROL WORD

CWHLD

t

CWSET

t

CWSTR

t

DATA BUS

CWSTR

VALID

RECEIVER OPERATON

DATA READY FLAG

D/R

ARINC DATA

BYTE SELECT

SEL

ENABLE BYTE ON BUS

EN

DATA BUS

BIT 31

BIT 32

SELEN

t

D/R

t

ENSEL

t

DATAEN

t

D/REN

t

END/R

t

EN

t

ENSEL

t

SELEN

t

DATAEN

t

ENDATA

t

ENDATA

t

ENEN

t

DON'T CARE

DON'T CARE

DON'T CARE

BYTE 1 VALID

BYTE 2 VALID

TIMING DIAGRAMS

HI-3282

HOLT INTEGRATED CIRCUITS

6