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HI-3582CJIF-10 Datasheet(PDF) 4 Page - Holt Integrated Circuits |
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HI-3582CJIF-10 Datasheet(HTML) 4 Page - Holt Integrated Circuits |
4 / 16 page vDD GND GND RIN1B OR RIN2B RIN1A OR RIN2A DIFFERENTIAL AMPLIFIERS ONES COMPARATORS NULL ZEROES vDD FIGURE 1. ARINC RECEIVER INPUT ARINC 429 DATA FORMAT Control register bit CR15 is used to control how individual bits in the received or transmitted ARINC word are mapped to the HI-3582/ HI-3583 data bus during data read or write operations. The following table describes this mapping: DATA BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BUS 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ARINC 13 12 11 10 9 31 30 32 12345678 BIT CR15=0 BYTE 1 ARINC 16 15 14 13 12 11 10 987654321 BIT CR15=1 BYTE 2 DATA BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BUS 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ARINC 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 BIT CR15=0 ARINC 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 BIT CR15=1 The HI-3582/HI-3583 guarantee recognition of these levels with a common mode Voltage with respect to GND less than ±4V for the worst case condition (3.0V supply and 13V signal level). The tolerances in the design guarantee detection of the above levels, so the actual acceptance ranges are slightly larger. If the ARINC signal is out of the actual acceptance ranges, including the nulls, the chip rejects the data. 1. Key to the performance of the timing checking logic is an accurate 1MHz clock source. Less than 0.1% error is recom- mended. 2. The sampling shift registers are 10 bits long and must show three consecutive Ones, Zeros or Nulls to be consid- ered valid data. Additionally, for data bits, the One or Zero in the upper bits of the sampling shift registers must be followed by a Null in the lower bits within the data bit time. For a Null in the word gap, three consecutive Nulls must be found in both the upper and lower bits of the sampling shift register. In this manner the minimum pulse width is guaranteed. 3. Each data bit must follow its predecessor by not less than 8 samples and no more than 12 samples. In this manner the bit rate is checked. With exactly 1MHz input clock frequency, the acceptable data bit rates are as follows: 83K BPS 10.4K BPS 125K BPS 15.6K BPS 4. The Word Gap timer samples the Null shift register every 10 input clocks (80 for low speed) after the last data bit of a valid reception. If the Null is present, the Word Gap counter is incremented. A count of 3 will enable the next reception. HIGH SPEED LOW SPEED DATA BIT RATE MIN DATA BIT RATE MAX RECEIVER LOGIC OPERATION BIT TIMING BIT RATE PULSE RISE TIME PULSE FALL TIME PULSE WIDTH Figure 2 shows a block diagram of the logic section of each receiver. The ARINC 429 specification contains the following timing specifi- cation for the received data: 100K BPS ± 1% 12K -14.5K BPS 1.5 ± 0.5 µsec 10 ± 5 µsec 1.5 ± 0.5 µsec 10 ± 5 µsec 5 µsec ± 5% 34.5 to 41.7 µsec The HI-3582/HI-3583 accept signals that meet these specifica- tions and rejects signals outside the tolerances. The way the logic operation achieves this is described below: HIGH SPEED LOW SPEED FUNCTIONAL DESCRIPTION (cont.) THE RECEIVERS ARINC BUS INTERFACE Figure 1 shows the input circuit for each receiver. The ARINC 429 specification requires the following detection levels: ONE +6.5 Volts to +13 Volts NULL +2.5 Volts to -2.5 Volts ZERO -6.5 Volts to -13 Volts STATE DIFFERENTIAL VOLTAGE HI-3582, HI-3583 HOLT INTEGRATED CIRCUITS 4 |
Similar Part No. - HI-3582CJIF-10 |
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Similar Description - HI-3582CJIF-10 |
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