EtronTech

8Mx16 DDR SDRAM

EM6A9160

8

Rev. 1.4

May 2006

•

CAS Latency Field (A6~A4)

This field specifies the number of clock cycles from the assertion of the Read command to

the first read data. The minimum whole value of CAS Latency depends on the frequency of

CK. The minimum whole value satisfying the following formula must be programmed into this

A6

A5

A4

CAS Latency

0

0

0

Reserved

0

0

1

Reserved

0

1

0

Reserved

0

1

1

3 clocks

1

0

0

4 clocks

1

0

1

Reserved

1

1

0

Reserved

1

1

1

Reserved

•

Test Mode field (A8~A7)

These two bits are used to enter the test mode and must be programmed to "00" in normal

operation.

A8

A7

Test Mode

0

0

Normal mode

1

0

DLL Reset

X

1

Test mode

•

( BS0, BS1)

BS1

BS0

An ~ A0

RFU

0

MRS Cycle

RFU

1

Extended Functions (EMRS)