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EM6A9325 Datasheet(PDF) 10 Page - Etron Technology, Inc.

Part # EM6A9325
Description  4M x 32 Low Power SDRAM (LPSDRAM)
Download  51 Pages
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Manufacturer  ETRON [Etron Technology, Inc.]
Direct Link  http://www.etron.com
Logo ETRON - Etron Technology, Inc.

EM6A9325 Datasheet(HTML) 10 Page - Etron Technology, Inc.

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EtronTech
4M x 32 LPSDRAM
EM6A9325
Preliminary
10
Rev 0.4
June 2003
CLK
COM M AND
T0
T1
T2T3
T4T5
T6T7
T8
DIN B2
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
WRITE B
NOP
DIN A0
DIN B0
DIN B1
DQ's
DIN B3
1 Clk Interval
Write Interrupted by a Write (Burst Length = 4, CAS# Latency = 1, 2, 3)
The Read command that interrupts a write burst without auto precharge function should be
issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid
data contention, input data must be removed from the DQs at least one clock cycle before the first
read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.
CLK
COMMAND
T0
T 1
T2T3
T4T5
T6T7
T8
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
READ B
NOP
DIN A0
don't care
DOUT B2
DOUT B0
DOUT B1
DOUT B3
DIN A0
don't care
don't care
DOUT B2
DOUT B0
DOUT B1
DOUT B3
Input data for the write is masked.
Input data must be removed from the DQ's at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
precharge function should be issued m cycles after the clock edge in which the last data-in element
is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the DQM
signals must be used to mask input data, starting with the clock edge following the last data-in
element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is
entered (refer to the following figure).
CLK
T0
T1
T2
T3T4T5
T6
WRITE
COMM AND
BANK (S)
ROW
NOP
NOP
Precharge
NOP
NOP
Activate
BA N K
COL n
DI N
n
DIN
n+1
DQM
ADDRESS
DQ
tWR
tRP
: don't care
Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge


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