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EM6A9325BG-7.5G Datasheet(PDF) 2 Page - Etron Technology, Inc. |
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EM6A9325BG-7.5G Datasheet(HTML) 2 Page - Etron Technology, Inc. |
2 / 51 page EtronTech 4M x 32 LPSDRAM EM6A9325 Preliminary 2 Rev 0.4 June 2003 Overview The EM6A9325 Hand-held LPSDRAM is a 128M bits high-speed CMOS synchronous DRAM with low power consumption organized as 1,048,576 words by 32 bits by 4 banks. The Hand-held functions are new features of the size of the memory array and the refresh period during Self-Refresh to be programmable by which the self refresh current is drastically reduced. High data transfer rate is achieved by the pipeline architecture with a synchronous interface, burst oriented Read and write accesse, muti banks operation and programmable burst lengths. The EM6A9325 provides Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. Through the programming burst type, burst length, CAS latency, and driving strength in mode register and extended mode register, a variety with high performance is fulfilled and useful in a variety of wide bandwidth, high performance and low power application. Block Diagram REFRESH COUN TER CO LU MN COUN TER ADDRESS BUFFER A0 A9 A1 0 A1 1 BA 0 BA 1 CO NTROL SIGN A L GE N ER A T OR DQ M0 ~ 3 CLO CK BUFFER CO MMA ND DECODER Column Decoder Sense Amplifier 4096 X 256 X 32 CELL ARRAY (BANK #0) Sense Amplifier Column Decoder 4096 X 256 X 32 CELL ARRAY (BANK #3) MO DE R E GIST ER CL K CKE CS # RA S# CA S# WE# A 10/ A P DQ 0 │ DQ 3 1 Sense Amplifier Column Decoder 4096X 256 X 32 CELL ARRAY (BANK #1) Sense Amplifier Column Decoder 4096 X 256 X 32 CELL ARRAY (BANK #2) DQ BUFFER |
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