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EM6A9320BI-3.6 Datasheet(PDF) 5 Page - Etron Technology, Inc.

Part # EM6A9320BI-3.6
Description  4M x 32 DDR SDRAM
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Manufacturer  ETRON [Etron Technology, Inc.]
Direct Link  http://www.etron.com
Logo ETRON - Etron Technology, Inc.

EM6A9320BI-3.6 Datasheet(HTML) 5 Page - Etron Technology, Inc.

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EtronTech
4Mx32 DDR SDRAM
EM6A9320
5
Rev 0.6
May. 2006
VSS
Supply Ground: Ground for the input buffers and core logic.
VDDQ
Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
VSSQ
Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
VREF
Supply Reference Voltage for Inputs: +0.5 x VDDQ
NC
-
No Connect: These pins should be left unconnected.
Note: The timing reference point for the differential clocking is the cross point of the CK and CK#. For any
applications using the single ended clocking, apply VREF to CK# pin.
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CK . Table 2
shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command
State
CKEn-1 CKEn DM BA1 BA0 A8 A11-A9, A7-0 CS# RAS# CAS# WE#
BankActivate
Idle(3)
H
X
X
V
V
Row Address
L
L
H
H
BankPrecharge
Any
H
X
X
V
V
L
X
L
L
H
L
PrechargeAll
Any
H
X
X
X
X
H
X
L
L
H
L
Write
Active(3)
H
X
V
V
V
L
L
H
L
L
Write and AutoPrecharge
Active(3)
H
X
V
V
V
H
L
H
L
L
Read
Active(3)
H
X
X
V
V
L
L
H
L
H
Read and Autoprecharge
Active(3)
H
X
X
V
V
H
Column
Address
A0~A7
L
H
L
H
Mode Register Set
Idle
H
X
X
L
L
L
L
L
L
Extended Mode Register Set
Idle
H
X
X
L
H
OP code
L
L
L
L
No-Operation
Any
H
X
X
X
X
X
X
L
H
H
H
Device Deselect
Any
H
X
X
X
X
X
X
H
X
X
X
Burst Stop
Active(4)
H
X
X
X
X
X
X
L
H
H
L
AutoRefresh
Idle
H
H
X
X
X
X
X
L
L
L
H
SelfRefresh Entry
Idle
H
L
X
X
X
X
X
L
L
L
H
H
X
X
X
SelfRefresh Exit
Idle
(Self Refresh)
L
H
X
X
X
X
X
L
H
H
H
H
X
X
X
Power Down Mode Entry Idle/Active(5)
H
L
X
X
X
X
X
L
H
H
H
H
X
X
X
Power Down Mode Exit
Any
(Power Down)
L
H
X
X
X
X
X
L
H
H
H
Data Write/
Output Enable
Active
H
X
L
X
X
X
X
X
X
X
X
Data Mask/
Output Disable
Active
H
X
H
X
X
X
X
X
X
X
X
Note: 1. V = Valid data, X = Don't Care, L = Low level, H = High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BA0, BA1signals.
4. Read burst stop with BST command for all burst types.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.


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