EM6AA320-XXMS datasheet(6/16 Pages) ETRON

6 page

EtronTech

8Mx32 DDR SDRAM

EM6AA320-XXMS

Rev 0.7

May. 2006

Mode Register Set (MRS)

The mode register is divided into various fields depending on functionality.

•

Burst Length Field (A2, A1, A0)

This field specifies the data length of column access and selects the Burst Length.

•

Addressing Mode Select Field (A3)

The Addressing Mode can be Interleave Mode or Sequential Mode. Both Sequential Mode and

Interleave Mode support burst length of 2, 4 and 8. Full page burst length is only for Sequential mode.

•

CAS# Latency Field (A6, A5, A4)

This field specifies the number of clock cycles from the assertion of the Read command to the first

read data. The minimum whole value of CAS# Latency depends on the frequency of CK. The

minimum whole value satisfying the following formula must be programmed into this field.

tCAC(min)

≦ CAS# Latency X tCK

•

Test Mode field :A7; DLL Reset Mode field : A8

These two bits must be programmed to "00" in normal operation.

•

( BA0, BA1)

Mode Resistor Bitmap

BA1

BA0

A11

A10

Mode RFU must be set to “0” DLL

CAS Latency

Burst Lenght

BA0

Mode

Type

MRS

Normal

Sequential

EMRS

Reset DLL

Interleave

Test Mode

CAS Latency

Burst Length

Reserved

3 clocks

4 clocks

All other Reserved

Full Page (Sequential)

All other Reserved

Burst Definition, Addressing Sequence of Sequential and Interleave Mode

Start Address

Burst Length

Sequential

Interleave

0, 1

1, 0

0, 1, 2, 3

1, 2, 3, 0

1, 0, 3, 2

2, 3, 0, 1

3, 0, 1, 2

3, 2, 1, 0

0, 1, 2, 3, 4, 5, 6, 7

1, 2, 3, 4, 5, 6, 7, 0

1, 0, 3, 2, 5, 4, 7, 6

2, 3, 4, 5, 6, 7, 0, 1

2, 3, 0, 1, 6, 7, 4, 5

3, 4, 5, 6, 7, 0, 1, 2

3, 2, 1, 0, 7, 6, 5, 4

4, 5, 6, 7, 0, 1, 2, 3

5, 6, 7, 0, 1, 2, 3, 4

5, 4, 7, 6, 1, 0, 3, 2

6, 7, 0, 1, 2, 3, 4, 5

6, 7, 4, 5, 2, 3, 0, 1

7, 0, 1, 2, 3, 4, 5, 6

7, 6, 5, 4, 3, 2, 1, 0

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