EtronTech

EM562161

Preliminary

10

Rev 1.0

July 2001

Write Cycle4

(UB#, LB# Controlled)(See Note 4)

tAS

A d d r e ss

tW C

t W P

t W R

W E #

t W HZ

tDS

t DH

tCW

tCW

tBW

C E 1 #

U B #

L B #

,

C E 2

D

O UT

D IN

(S e e No te 5)

V AL I D DA T A IN

t BLZ

tLZ

Note:

1. WE# remains HIGH for the read cycle.

2. If CE1# goes LOW (or CE2 goes HIGH) with or after WE# goes LOW, the outputs will remain at high

impedance.

3. If CE1# goes HIGH (or CE2 goes LOW) coincident with or before WE# goes HIGH, the outputs will remain at

high impedance.

4. If OE# is HIGH during the write cycle, the outputs will remain at high impedance.

5. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be

applied.