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AM29BDD160GB65AKI Datasheet(PDF) 11 Page - Advanced Micro Devices |
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AM29BDD160GB65AKI Datasheet(HTML) 11 Page - Advanced Micro Devices |
11 / 79 page ![]() June 7, 2006 Am29BDD160G 9 PIN CONFIGURATION A–1 = Least significant address bit for the 16-bit data bus, and selects between the high and low word. A –1 is not used for the 32-bit mode (WORD# = V IH). A0–A18 = 19-bit address bus for 16 Mb device. A9 supports 12 V autoselect inputs. DQ0–DQ31= 32-bit data inputs/outputs/float WORD# = Selects 16-bit or 32-bit mode. When WORD# = V IH, data is output on DQ31–DQ0. When WORD# = VIL, data is output on DQ15–DQ0. CE# = Chip Enable Input. This signal is asynchro- nous relative to CLK for the burst mode. OE# = Output Enable Input. This signal is asyn- chronous relative to CLK for the burst mode. WE# = Write enable. This signal is asynchronous relative to CLK for the burst mode. V SS = Device ground NC = Pin not connected internally RY/BY# = Ready/Busy output and open drain. When RY/BY# = VIH, the device is ready to ac- cept read operations and commands. When RY/BY# = V OL, the device is either executing an embedded algorithm or the device is executing a hardware reset oper- ation. CLK = Clock Input that can be tied to the system or microprocessor clock and provides the fundamental timing and internal operating frequency. ADV# = Load Burst Address input. Indicates that the valid address is present on the address inputs. IND# = End of burst indicator for finite bursts only. IND is low when the last word in the burst sequence is at the data outputs. WAIT# = Provides data valid feedback only when the burst length is set to continuous. WP# = Write Protect input. When WP# = VOL, the two outermost bootblock sector in the 75% bank are write protected regardless of other sector protection configurations. ACC = Acceleration input. When taken to 12 V, program and erase operations are acceler- ated. When not used for acceleration, ACC = V SS to VCC. V IO (VCCQ)= Output Buffer Power Supply (1.65 V to 2.75 V) V CC = Chip Power Supply (2.5 V to 2.75 V) RESET# = Hardware reset input LOGIC SYMBOLS x16 Mode x32 Mode 20 16 DQ0–DQ15 A-1 to A18 CLK RY/BY# IND/WAIT# CE# OE# WE# RESET# ADV# ACC WP# V IO (VCCQ) WORD# 19 32 DQ0–DQ31 A0–A18 CLK RY/BY# IND/WAIT# CE# OE# WE# RESET# ADV# ACC WP# V IO (VCCQ) WORD# |
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