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LVT22V10-7N Datasheet(PDF) 2 Page - NXP Semiconductors |
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LVT22V10-7N Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 20 page Philips Semiconductors Product specification LVT22V10 3V high speed, universal PLD device 2 1998 Feb 10 853-1759 18947 FEATURES • Fastest 3V PLD • Supports 3/5V mixed systems • Low ground bounce (<1.1V worst case) • Live insertion/extraction permitted • Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs • Metastable hardened device • High output drive capability: 32mA/–16mA • Varied product term distribution with up to 16 product terms per output for complex functions • Programmable output polarity • Available in 300 mil-wide 24-pin Plastic Small Outline Package • Design support provided for third party CAD development and programming hardware DESCRIPTION The LVT22V10 is a versatile PAL ® device fabricated on the Philips BiCMOS QUBiC process. The QUBiC process produces very high speed 3V devices (7.5ns) which have excellent noise characteristics. Ground bounce of an output held low while the remaining 9 outputs switch from high to low is typically less than 0.7V. VCC bounce of an output held high while the remaining 9 outputs switch from low to high is typically less than 1.0V. The LVT22V10 was designed to support mixed 3/5V systems. The inputs are capable of handling 7V while the outputs can be pulled up to 7V. The designer can interface directly from 5V outputs (CMOS full rail or totem pole) to a 3V LVT input. A 3V LVT output can drive a 5V TTL input directly, or in the case of a CMOS input, the LVT output can interface with the use of an external pull-up resistor. Finally, no external pull-up resistors are needed on unused input pins due to a bus-hold data structure designed into the LVT input. The LVT22V10 has been designed with high drive outputs (32mA sink and 16mA source currents), which allows for direct connection to a backplane bus. This feature eliminates the need for additional, standalone bus drivers, which are traditionally required to boost the drive of a standard PLDs. The LVT22V10 outputs are designed to support Live Insertion/Extraction into powered up systems. The output is specially designed so that during VCC ramp, the output remains 3-Stated until VCC [ 2.1V. At that time the outputs become fully functional depending upon device inputs. (See DC Electrical Characteristics, Symbol IPU/PD, Page 5). In addition when an LVT22V10 output is tied to a 5V bus, no bus current is loaded. The LVT22V10 uses the familiar AND/OR logic array structure, which allows direct implementation of sum-of-products equations. This device has a programmable AND array which drives a fixed OR array. The OR sum of products feeds an “Output Macro Cell” (OMC) which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback. PIN CONFIGURATIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 D and N Packages I0/CLK I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 VCC F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 I11 GND NC NC A Package (standard) NC CLK/ I0 I1 I2 I3 I4 I5 GND I6 I8 I9 I10 GND I11 F0 F1 F2 F3 F7 F6 F5 F4 F8 F9 VCC A = Plastic Leaded Chip Carrier N = Plastic Dual In-Line Package (300mil-wide) D = Plastic Small Outline Large (300mil-wide) Package SP00436 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 A Package (evolutionary) CLK/ I0 I1 I2 I3 I4 I5 I6 I8 I9 I10 GND I11 F0 F1 F2 F3 F7 F6 F5 F4 F8 F9 VCC A = Plastic Leaded Chip Carrier GND VCC GND GND I7 ®PAL is a registered trademark of Advanced Micro Devices, Inc. |
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