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HFA1212IB Datasheet(PDF) 5 Page - Intersil Corporation

Part # HFA1212IB
Description  Dual 350MHz, Low Power Closed Loop Buffer Amplifier
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

HFA1212IB Datasheet(HTML) 5 Page - Intersil Corporation

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5
Unity Gain Considerations
Unity gain selection is accomplished by floating the -Input of
the HFA1212. Anything that tends to short the -Input to
GND, such as stray capacitance at high frequencies, will
cause the amplifier gain to increase toward a gain of +2. The
result is excessive high frequency peaking, and possible
instability. Even the minimal amount of capacitance
associated with attaching the -Input lead to the PCB results
in approximately 6dB of gain peaking. At a minimum this
requires due care to ensure the minimum capacitance at the
-Input connection.
Table 1 lists five alternate methods for configuring the
HFA1212 as a unity gain buffer, and the corresponding
performance. The implementations vary in complexity and
involve performance trade-offs. The easiest approach to
implement is simply shorting the two input pins together, and
applying the input signal to this common node. The amplifier
bandwidth decreases from 430MHz to 280MHz, but
excellent gain flatness is the benefit. A drawback to this
approach is that the amplifier input noise voltage and input
offset voltage terms see a gain of +2, resulting in higher
noise and output offset voltages. Alternately, a 100pF
capacitor between the inputs shorts them only at high
frequencies, which prevents the increased output offset
voltage but delivers less gain flatness.
Another straightforward approach is to add a 620W resistor
in series with the amplifier’s positive input. This resistor and
the HFA1212 input capacitance form a low pass filter which
rolls off the signal bandwidth before gain peaking occurs.
This configuration was employed to obtain the data sheet
AC and transient parameters for a gain of +1.
Pulse Overshoot
The HFA1212 utilizes a quasi-complementary output stage
to achieve high output current while minimizing quiescent
supply current. In this approach, a composite device
replaces the traditional PNP pulldown transistor. The
composite device switches modes after crossing 0V,
resulting in added distortion for signals swinging below
ground, and an increased overshoot on the negative portion
of the output waveform (see Figure 6, Figure 9, and Figure
12). This overshoot isn’t present for small bipolar signals
(see Figure 4, Figure 7, and Figure 10) or large positive
signals (see Figure 5, Figure 8 and Figure 11).
PC Board Layout
This amplifier’s frequency response depends greatly on the
care taken in designing the PC board (PCB). The use of low
inductance components such as chip resistors and chip
capacitors is strongly recommended, while a solid
ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10
µF) tantalum in parallel with a small value
(0.1
µF) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
An example of a good high frequency layout is the
Evaluation Board shown in Figure 3.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (RS) in series with the output
prior to the capacitance.
Figure 1 details starting points for the selection of this
resistor. The points on the curve indicate the RS and CL
combinations for the optimum bandwidth, stability, and
settling time, but experimental fine tuning is recommended.
Picking a point above or to the right of the curve yields an
overdamped response, while points below or left of the curve
indicate areas of underdamped performance.
RS and CL form a low pass network at the output, thus
limiting system bandwidth well below the amplifier bandwidth
of 350MHz. By decreasing RS as CL increases (as illustrated
in the curves), the maximum bandwidth is obtained without
sacrificing stability. In spite of this, bandwidth decreases as
the load capacitance increases.
TABLE 1. UNITY GAIN PERFORMANCE FOR VARIOUS
IMPLEMENTATIONS
APPROACH
PEAKING
(dB)
BW
(MHz)
±0.1dB GAIN
FLATNESS (MHz)
Remove -IN Pin
4.5
430
21
+RS = 620Ω
0
220
27
+RS = 620Ω and
Remove -IN Pin
0.5
215
15
Short +IN to -IN (e.g.,
Pins 2 and 3)
0.6
280
70
100pF Capacitor
Between +IN and -IN
0.7
290
40
HFA1212


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