8

Theory of Operation

The HI5810 is a CMOS 12-bit, Analog-to-Digital Converter

that uses capacitor charge balancing to successively

approximate the analog input. A binarily weighted capacitor

network forms the A/D heart of the device. See the block

diagram for the HI5810.

The capacitor network has a common node which is

connected to a comparator. The second terminal of each

During the first three clock periods of a conversion cycle, the

switchable end of every capacitor is connected to the input

and the comparator is being auto balanced at the capacitor

common node.

During the fourth period, all capacitors are disconnected

from the input; the one representing the MSB (D11) is

charges balance out, will indicate whether the input was

period, the comparator output is stored and the MSB

At the end of periods 5 through 14, capacitors representing

D10 through D1 are tested, the result stored, and each

At the end of the 15th period, when the LSB (D0) capacitor is

tested, (D0) and all the previous results are shifted to the

output registers and drivers. The capacitors are reconnected

to the input, the comparator returns to the balance state, and

the data ready output goes active. The conversion cycle is

now complete.

Analog Input

The analog input pin is a predominately capacitive load that

changes between the track and hold periods of the

conversion cycle. During hold, clock period 4 through 15, the

input loading is leakage and stray capacitance, typically less

than 5

µA and 20pF.

At the start of input tracking, clock period 1, some charge is

dumped back to the input pin. The input source must have low

enough impedance to dissipate the current spike by the end of

the tracking period as shown in Figure 13. The amount of

charge is dependent on supply and input voltages. The

average current is also proportional to clock frequency.

As long as these current spikes settle completely by end of

the signal acquisition period, converter accuracy will be

preserved. The analog input is tracked for 3 clock cycles.

With an external clock of 1.5MHz the track period is 2

µs.

A simplified analog input model is presented in Figure 14.

380pF capacitor being charged through a 420

Ω internal

TABLE 1. PIN DESCRIPTIONS

PIN NO.

NAME

DESCRIPTION

1

DRDY

Output flag signifying new data is available.

Goes high at end of clock period 15. Goes low

when new conversion is started.

2

D0

Bit 0 (Least Significant Bit, LSB).

3D1

Bit 1.

4D2

Bit 2.

5D3

Bit 3.

6D4

Bit 4.

7D5

Bit 5.

8D6

Bit 6.

9D7

Bit 7.

10

D8

Bit 8.

11

D9

Bit 9.

12

Digital Ground, (0V).

13

D10

Bit 10.

14

D11

Bit 11 (Most Significant Bit, MSB)

15

OEM

Three-State Enable for D4-D11. Active low

input.

16

Analog Ground, (0V).

17

18

Analog Input.

19

code end of input range.

20

code end of input range.

21

STRT

Start Conversion Input active low, recognized

after end of clock period 15.

22

CLK

CLK Input or Output. Conversion functions are

synchronized to positive going edge (see text).

23

OEL

Three-State Enable for D0 D3. Active low input.

24

Digital Positive Supply (+5V).

20mA

10mA

0mA

5V

0V

5V

0V

CLK

DRDY

200ns/DIV.

FIGURE 13. TYPICAL ANALOG INPUT CURRENT

HI5810