10

Again, the difference between the two internal voltage

significant change in ADC performance. The simplest way to

HI5805.

The single ended analog input can be DC coupled (Figure

18) as long as the input is within the analog input common

mode voltage range.

The resistor, R, in Figure 18 is not absolutely necessary but

may be used as a load setting resistor. A capacitor, C,

frequency noise on the inputs, also improving performance.

Values around 20pF are sufficient and can be used on AC

coupled inputs as well. Note, however, that the value of

capacitor C chosen must take into account the highest

frequency component of the analog input signal.

A single ended source will give better overall system

performance if it is first converted to differential before

driving the HI5805.

Digital I/O and Clock Requirements

The HI5805 provides a standard high-speed interface to

external TTL/CMOS logic families. The digital CMOS clock

input has TTL level thresholds. The low input bias current

allows the HI5805 to be driven by CMOS logic.

The digital CMOS outputs have a separate digital supply.

This allows the digital outputs to operate from a 3.0V to 5.0V

supply. When driving CMOS logic, the digital outputs will

swing to the rails. When driving standard TTL loads, the

digital outputs will meet standard TTL level requirements

even with a 3.0V supply.

In order to ensure rated performance of the HI5805, the duty

cycle of the clock should be held at 50%

±5%. It must also

have low jitter and operate at standard TTL levels.

Performance of the HI5805 will only be guaranteed at

conversion rates above 0.5MSPS. This ensures proper

performance of the internal dynamic circuits.

Supply and Ground Considerations

The HI5805 has separate analog and digital supply and

ground pins to keep digital noise out of the analog signal

path. The part should be mounted on a board that provides

separate low impedance connections for the analog and

digital supplies and grounds. For best performance, the

supplies to the HI5805 should be driven by clean, linear

regulated supplies. The board should also have good high

frequency decoupling capacitors mounted as close as

possible to the converter. If the part is powered off a single

supply then the analog supply and ground pins should be

isolated by ferrite beads from the digital supply and ground

pins.

Refer to the Application Note AN9214, “Using Intersil High

Speed A/D Converters” for additional considerations when

using high speed converters.

Static Performance Definitions

above half scale. Offset is defined as the deviation of the

actual code transition from this point.

Full-Scale Error (FSE)

The last code transition should occur for an analog input that

removed. Full-scale error is defined as the deviation of the

actual code transition from this point.

Differential Linearity Error (DNL)

DNL is the worst case deviation of a code width from the

ideal value of 1 LSB.

Integral Linearity Error (INL)

INL is the worst case deviation of a code center from a best

fit straight line calculated from the measured data.

Power Supply Rejection Ratio (PSRR)

Each of the power supplies are moved plus and minus 5%

and the shift in the offset and gain error (in LSBs) is noted.

HI5805

VDC

FIGURE 17. AC COUPLED SINGLE ENDED INPUT

HI5805

R

C

FIGURE 18. DC COUPLED SINGLE ENDED INPUT

HI5805