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USB2227-NU-05 Datasheet(PDF) 11 Page - SMSC Corporation |
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USB2227-NU-05 Datasheet(HTML) 11 Page - SMSC Corporation |
11 / 27 page 4th Generation USB2.0 Flash Media Controller with Integrated Card Power FETs Datasheet SMSC USB2227/USB2228 11 Revision 1.91 (10-13-06) DATASHEET Chapter 5 Pin Descriptions This section provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The “n” symbol in the signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When “n” is not present before the signal name, the signal is asserted when at the high voltage level. The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of “active low” and “active high” signal. The term assert, or assertion indicates that a signal is active, independent of whether that level is represented by a high or low voltage. The term negate, or negation indicates that a signal is inactive. 5.1 PIN Descriptions SYMBOL 128-PIN VTQFP 124-PIN DQFN BUFFER TYPE DESCRIPTION CompactFlash (In True IDE mode) INTERFACE CF_nCS1 61 A31 O8PU CF Chip Select 1: This pin is the active low chip select 1 signal for the CF ATA device. CF_nCS0 60 B28 O8PU CF Chip Select 0: This pin is the active low chip select 0 signal for the task file registers of CF ATA device in the True IDE mode. CF_SA2 64 B30 O8 CF Register Address 2: This pin is the register select address bit 2 for the CF ATA device. CF_SA1 63 A32 O8 CF Register Address 1: This pin is the register select address bit 1 for the CF ATA device. CF_SA0 62 B29 O8 CF Register Address 0: This pin is the register select address bit 0 for the CF ATA device. CF_IRQ 55 B26 IPD CF Interrupt: This is the active high interrupt request signal from the CF device. CF_D[15:8] 52 51 50 48 46 45 41 40 A26 B24 A25 A24 B22 A23 A21 A20 I/O8PD CF Data 15-8: The bi-directional data signals CF_D15-CF_D8 in True IDE mode data transfer. In the True IDE Mode, all of task file register operation occur on the CF_D[7:0], while the data transfer is on CF_D[15:0]. The bi-directional data signal has an internal weak pull- down resistor. |
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