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COM20051I Datasheet(PDF) 8 Page - SMSC Corporation |
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COM20051I Datasheet(HTML) 8 Page - SMSC Corporation |
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8 / 74 page  SMSC DS – COM20051I Page 8 Rev. 03/27/2000 BASIC ARCHITECTURE The COM20051I consists of four functional blocks: the 80C32 microcontroller core, ARCNET network cell (includes 1K of buffer RAM), programmable address decoder, and programmable interrupt router. The internal architecture of the COM20051I is shown in Figure 1. The 80C32 microcontroller is a full ROMless implementation of the popular Intel 8051 series. The ARCNET network core is similar in architecture to SMSC's popular COM20020 family of ARCNET controllers and retains the same command and status flags of previous ARCNET controllers. The programmable address decoder maps the ARCNET registers into a 256-byte page anywhere within the External Data Memory space of the 80C32. The ARCNET core was mapped to the External Data Memory space to simplify software and application development and for production test purposes. ARCNET core is available to the developer when working with the 8051 emulator. When the COM20051I is put into Emulate mode, the internal microcontroller is put into a high impedance state, thus allowing an external In-Circuit Emulator (ICE) to program the ARCNET core. The advantage of this approach versus mapping the ARCNET registers into the internal memory (Special Function) area of the 80C32 is that dedicated software development tools will not be necessary to debug application software. Since a majority of 8051 applications use only a small portion of the Data Memory space, there is no penalty paid for used address space. There will also be no penalty in execution time, since cycle times for external data memory accesses and internal direct memory moves are identical. The network interrupt can be routed to either of the two external interrupt ports or can be assigned to one of the general purpose I/O ports. The ARCNET interrupt is internally wire ORed with the external interrupt pin to allow greater system flexibility. 80C32 ARCHITECTURE AND INSTRUCTION SET The 80C32 microcontroller core is identical to the 16MHz Intel 80C32 in all respects except for the absence of Timer 2. Please refer to the Intel Embedded Microcontrollers and Processors Databook, Volume 1, for details regarding the 8051 architecture, peripherals, instruction set, and programming guide. Note that any access to the internal ARCNET core or any external memorry access is visible on the pins of the COM20051I. The following differences apply to the COM20051I: 1. Oscillator frequency is 40MHz instead of 16MHz. This is necessary to derive a 20MHz clock for the ARCNET core. The processor still operates at 16MHz. 2. nEA pin - This pin must be tied to ground for normal internal processor operation. When tied to VCC, the COM20051I will enter the Emulate mode. 3. Unused pins - The COM20051I is packaged in a 44-pin PLCC. Network I/O is generated on the four unused pins of the standard 80C32 PLCC package. No DIP package is available. 4. Power Down operation - The Power Down mode can only be used in conjunction when the internal oscillator is being used. If an external oscillator is used and the Power Down mode is invoked, damage may result to the oscillator and to the COM20051I. Clock Speed The COM20051I processor operates at 16MHz and the network controller at a maximum 40MHz clock rate. A single crystal oscillator is used to supply the two clocks: a 16MHz processor clock and a 20MHz network clock for the nominal 2.5 Mbps data rate. Pins 20 and 21 are designated as crystal inputs. When clocking with an external oscillator, pin 21 (XTAL1) functions as the clock input. Emulate Mode The COM20051I contains a unique feature called the Emulate mode that most 8051-based peripheral devices do not accommodate. TheEmulate mode permits developers to access and program the internal ARCNET core using a standard low-cost 8032 emulator. This feature eliminates the need for expensive dedicated development equipment needed for other types of 8051-based peripheral devices. The Emulate mode is invoked by connecting the nEA pin to VCC. This causes the internal 80C32 processor to enter a HI-Z state and changes the state of the COM20051I pins according to the following table: |
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