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HI3304JIP Datasheet(PDF) 2 Page - Intersil Corporation |
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HI3304JIP Datasheet(HTML) 2 Page - Intersil Corporation |
2 / 12 page 2 Functional Block Diagram †Cascaded Auto Balance (CAB) NOTE: CE1 and CE2 inputs and data outputs have standard CMOS protection networks to VDD and VSS. Analog inputs and clock have standard CMOS protection networks to VAA+ and VAA-. 9 7 1 DQ CLK DQ CLK DQ CLK DQ CLK DQ CLK DQ CLK 5 2 3 4 6 ENCODER LOGIC ARRAY D LATCH 16 Q COUNT 16 COUNT 8 D LATCH 8 Q D LATCH 0 Q COUNT 1 8 14 VAA-VSS †CAB COMPARATOR #1 φ1 (AUTO BALANCE) φ2 (SAMPLE UNKNOWN) 50k Ω CLOCK 15 13 VREF- VREF+ VIN 11 16 10 VAA+VDD φ1 φ1 φ1 φ1 φ2 φ2 1/ 2R 1/ 2R R R R †CAB #8 †CAB #16 OUTPUT REGISTER THREE-STATE DRIVERS DATA CHANGE OVERFLOW BIT 4 BIT 3 BIT 2 BIT 1 (LSB) CE1 CE2 R 12 HI3304 HI3304 |
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