9

Continuous Clock Operation

One complete conversion cycle can be traced through the

HI3304 via the following steps. (Refer to timing diagram

Figure 3). The rising edge of the clock input will start a

“sample” phase. During this entire “High” state of the clock,

the 16 comparators will track the input voltage and the 16

latches will track the comparator outputs. At the falling edge

of the clock, all 16 comparator outputs are captured by the

16 latches. This ends the “sample” phase and starts the

“auto balance” phase for the comparators. During this “Low”

state of the clock the output of the latches propagates

through the decode array and a 6-bit code appears at the D

inputs of the output registers. On the next rising edge of the

clock, this 6-bit code is shifted into the output registers and

three-state drivers. This also marks the start of a new

“sample” phase, thereby repeating the conversion process

for this next cycle.

Pulse Mode Operation

For sampling high speed nonrecurrent or transient data, the

converter may be operated in a pulse mode in one of three

ways. The fastest method is to keep the converter in the

Sample Unknown phase,

φ2, during the standby state. The

device can now be pulsed through the Auto Balance phase

with as little as 20ns. The analog value is captured on the

leading edge of

φ1 and is transferred into the output registers

on the trailing edge of

φ1. We are now back in the standby

state,

φ2, and another conversion can be started within

20ns, but not later than 5

µs due to the eventual droop of the

commutating capacitors. Another advantage of this method

is that it has the potential of having the lowest power drain.

The larger the time ratio between

φ2 and φ1, the lower the

power consumption. (See Timing Diagram Figure 3A).

The second method uses the Auto Balance phase,

φ1, as

the standby state. In this state the converter can stay

indefinitely waiting to start a conversion. A conversion is

performed by strobing the clock input with two

φ2 pulses.

The first pulse starts a Sample Unknown phase and

captures the analog value in the comparator latches on the

trailing edge. A second

φ2 pulse is needed to transfer the

date into the output registers. This occurs on the leading

edge of the second pulse. The conversion now takes place

in 40ns, but the repetition rate may be as slow as desired.

The disadvantage to this method is the slightly higher device

dissipation due to the low ratio of

φ2 to φ1. (See Timing

Diagram Figure 3B).

For applications requiring both indefinite standby and lowest

power, standby can be in the

φ2 (Sample Unknown) state

with two

φ1 pulses to generate valid data (see Figure 3C).

The conversion process now takes 60ns. [Note that the

Increased Accuracy

In most case the accuracy of the HI3304 should be sufficient

without any adjustments. In applications where accuracy is

of utmost importance, two adjustments can be made to

obtain better accuracy; i.e., offset trim and gain trim.

Offset Trim

In general offset correction can be done in the preamp cir-

be adjusted to produce an offset trim.

The theoretical input voltage to produce the first transition is

Adjust offset by applying this input voltage and adjusting the

alternating between 0 and 1 occurs.

Gain Trim

In general the gain trim can also be done in the preamp circuitry

by introducing a gain adjustment for the op amp. When this is

not possible, then a gain adjustment circuit should be made to

To perform the gain trim, first do the offset trim and then

Layout, Input and Supply Considerations

The HI3304 should be mounted on a ground-planed,

printed-circuit board, with good high-frequency decoupling

capacitors mounted as close as possible. If the supply is

The HI3304 outputs current spikes to its input at the start of

the

auto-balance

and

sample

clock

phases.

A

low

impedance source, such as a locally-terminated 50

Ω coax

cable, should be used to drive the input terminal. A fast-

settling buffer such as the HA-5033, HA-5242, or CA3450

terminals also have current spikes, and should be well

bypassed.

Care should be taken to keep digital signals away from the

analog input, and to keep digital ground currents away from

the analog ground. If possible, the analog ground should be

connected to digital ground only at the HI3304.

Bipolar Operation

potential also to be negative. Figure 12B shows operation

for an input range above the digital supply.

HI3304

HI3304